公开(公告)号：US20230328951A1

公开(公告)日：2023-10-12

申请号：US18097675

申请日：2023-01-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DONG-SIK PARK ,  SOOHO SHIN ,  CHEOLHO BAEK

IPC: H10B12/00

CPC classification number: H10B12/033 ,  H10B12/50 ,  H10B12/315

Abstract: A semiconductor device may include a substrate including a cell array region, a data storage structure provided on the cell array region of the substrate, the data storage structure including a bottom electrode, a top electrode on the bottom electrode, and a dielectric layer interposed between the bottom electrode and the top electrode, a blocking layer provided on a top surface of the top electrode, a lower interlayer insulating layer provided on the blocking layer, and a lower contact penetrating the lower interlayer insulating layer and electrically connected to the top electrode. At least a portion of a side surface of the lower contact may contact the blocking layer.

公开(公告)号：US20230146012A1

公开(公告)日：2023-05-11

申请号：US17954394

申请日：2022-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYEON-WOO JANG ,  DONG-WAN KIM ,  Keonhee PARK ,  DONG-SIK PARK ,  SOOHO SHIN ,  JIHOON CHANG

IPC: H01L27/108 ,  G11C5/06

CPC classification number: H01L27/10814 ,  G11C5/063 ,  H01L27/10823 ,  H01L27/10897

Abstract: Disclosed are semiconductor memory devices and their fabrication methods. The semiconductor memory device comprises a semiconductor substrate that includes a cell array region and a peripheral region, a plurality of bottom electrodes on the semiconductor substrate on the cell array region, a dielectric layer that conformally covers sidewalls and top surfaces of the bottom electrodes, and a top electrode on the dielectric layer and between the bottom electrodes. The top electrode includes a first metal layer, a silicon-germanium layer, a second metal layer, and a silicon layer that are sequentially stacked. An amount of boron in the silicon-germanium layer is greater than an amount of boron in the silicon layer.

公开(公告)号：US20230041059A1

公开(公告)日：2023-02-09

申请号：US17857395

申请日：2022-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： DONG-WAN KIM ,  Keonhee PARK ,  DONG-SIK PARK ,  Joonsuk PARK ,  JIHOON CHANG ,  HYEON-WOO JANG

IPC: H01L27/108

Abstract: A semiconductor device may include a substrate including a cell region, a peripheral region, and a boundary region between the cell region and the peripheral region, bit lines provided on the cell region and extended in a first direction parallel to a top surface of the substrate, bit line capping patterns provided on the bit lines, and a boundary pattern provided on the boundary region. End portions of the bit lines may be in contact with a first interface of the boundary pattern, and the bit line capping patterns may include the same material as the boundary pattern.

公开(公告)号：US20250016988A1

公开(公告)日：2025-01-09

申请号：US18424577

申请日：2024-01-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DONG-SIK PARK ,  JAE WON NA ,  JIHEE JUN

IPC: H10B12/00

Abstract: A semiconductor device includes a substrate including cell array and peripheral regions, a bit line positioned in the cell array region and extending in a first direction, a shielding line extending in the first direction from the cell array region to the peripheral region and positioned adjacent to the bit line in a second direction crossing the first direction, a shielding contact line positioned in the peripheral region, extending in the second direction, and connected to the shielding line, a channel pattern positioned on the bit line and extending in a direction vertical from the bit line, a word line extending in the second direction and positioned on the channel pattern, a gate insulation pattern positioned between the channel pattern and the word line, an insulation pattern positioned on the word line, a landing pad connected to the channel pattern, and a data storage pattern connected to the landing pad.

公开(公告)号：US20170256411A1

公开(公告)日：2017-09-07

申请号：US15447969

申请日：2017-03-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DONG-SIK PARK ,  Won-Chul Lee

IPC: H01L21/30 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L29/34

CPC classification number: H01L21/3003 ,  H01L21/76816 ,  H01L21/76849 ,  H01L21/76852 ,  H01L23/485 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329 ,  H01L27/10894 ,  H01L28/90 ,  H01L29/34

Abstract: A semiconductor device includes a substrate; a hydrogen insulating layer disposed on the substrate and including hydrogen ions; a first level layer disposed on the substrate and including a first wire and a second wire; a second level layer disposed on the substrate at a different level from the first level layer and including a third wire; an interlayer insulating layer disposed between the first level layer and the second level layer; a diffusion prevention layer contacting the third wire; a contact plug penetrating the interlayer insulating layer and electrically connecting the second wire to the third wire; and a dummy contact plug penetrating the interlayer insulating layer. The dummy contact plug contacts the first and second level layers, is spaced apart from the diffusion prevention layer, and is configured to provide a movement path for the hydrogen ions in the hydrogen insulating layer.