公开(公告)号：US09165672B2

公开(公告)日：2015-10-20

申请号：US14077606

申请日：2013-11-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongku Kang ,  Dae Yeal Lee

IPC: G11C11/34 ,  G11C16/34 ,  G11C16/26 ,  G11C7/10 ,  G11C17/06

CPC classification number: G11C16/3459 ,  G11C7/1039 ,  G11C11/56 ,  G11C16/06 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3481 ,  G11C17/06

Abstract: A nonvolatile memory device is provided which includes a cell array including a plurality of memory cells; a page buffer unit including a plurality of page buffers and configured to sense whether programming of selected memory cells is completed, at a program verification operation; and a control logic configured to provide a set pulse for setting data latches of each of the page buffers to a program inhibit state according to the sensing result, wherein the control logic provides the set pulse to at least two different page buffers such that data latches of the at least two different page buffers are set.

Abstract translation: 提供一种包括包括多个存储单元的单元阵列的非易失性存储器件; 页面缓冲器单元，其包括多个页缓冲器，并且被配置为在程序验证操作时检测所选存储单元的编程是否完成; 以及控制逻辑，被配置为根据感测结果提供用于将每个页缓冲器的数据锁存器设置为编程禁止状态的设置脉冲，其中控制逻辑将设置脉冲提供给至少两个不同的页缓冲器，使得数据锁存 设置至少两个不同页面缓冲器。

公开(公告)号：US20190035478A1

公开(公告)日：2019-01-31

申请号：US15957149

申请日：2018-04-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae Yeal Lee ,  Jaewoo Im ,  Jae-Hak Yun ,  Kangguk Lee

IPC: G11C16/30

Abstract: A method of operating a nonvolatile memory device is provided. The nonvolatile memory device includes a memory cell array including a plurality of memory cells. The method includes: the nonvolatile memory device determining an operation mode based on the received command, the nonvolatile memory device generating a comparison voltage based on the determined operation mode, the nonvolatile memory device comparing the comparison voltage with a reference voltage to generate a result, and the nonvolatile memory device performing a recovery operation on at least one of the memory cells depending on the result.

公开(公告)号：US10522230B2

公开(公告)日：2019-12-31

申请号：US15957149

申请日：2018-04-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae Yeal Lee ,  Jaewoo Im ,  Jae-Hak Yun ,  Kangguk Lee

IPC: G11C16/30 ,  G11C5/14 ,  G11C7/04 ,  G11C11/56 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/34 ,  G11C16/04

Abstract: A method of operating a nonvolatile memory device is provided. The nonvolatile memory device includes a memory cell array including a plurality of memory cells. The method includes: the nonvolatile memory device determining an operation mode based on the received command, the nonvolatile memory device generating a comparison voltage based on the determined operation mode, the nonvolatile memory device comparing the comparison voltage with a reference voltage to generate a result, and the nonvolatile memory device performing a recovery operation on at least one of the memory cells depending on the result.

公开(公告)号：US09520201B2

公开(公告)日：2016-12-13

申请号：US14853488

申请日：2015-09-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongku Kang ,  Dae Yeal Lee

IPC: G11C11/34 ,  G11C16/34 ,  G11C16/26 ,  G11C7/10 ,  G11C16/06 ,  G11C17/06 ,  G11C11/56 ,  G11C16/10 ,  G11C16/24

CPC classification number: G11C16/3459 ,  G11C7/1039 ,  G11C11/56 ,  G11C16/06 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3481 ,  G11C17/06

Abstract: A nonvolatile memory device is provided which includes a page buffer unit. The page buffer unit includes a first page buffer including a first A latch configured to store first upper bit data and a first B latch configured to store first lower bit data, and a second page buffer including a second A latch configured to store second upper bit data and a second B latch configured to store second lower bit data. A set pulse may be applied to both the first A latch and the second B latch, or to both the second A latch and the first B latch. The non-volatile memory device may provide high write performance and may respond within a time out period of a handheld terminal.

Abstract translation: 提供了一种非易失性存储器件，其包括页缓冲器单元。 页面缓冲器单元包括第一页缓冲器，其包括被配置为存储第一高位数据的第一A锁存器和被配置为存储第一低位数据的第一B锁存器，以及包括第二A锁存器的第二页缓冲器，其被配置为存储第二高位 数据和第二B锁存器，其被配置为存储第二低位数据。 设定的脉冲可以施加到第一A锁存器和第二B锁存器，或者施加到第二A锁存器和第一B锁存器两者。 非易失性存储器件可以提供高写入性能并且可以在手持终端的超时周期内进行响应。