公开(公告)号：US20240161824A1

公开(公告)日：2024-05-16

申请号：US18503719

申请日：2023-11-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungmin LEE ,  Youngkeol KIM ,  Daeshik KIM

IPC: G11C13/00

CPC classification number: G11C13/0064 ,  G11C13/004 ,  G11C13/0069

Abstract: A memory device including a memory cell including a variable resistance element, a controller configured to generate a control signal based on whether the memory device performs a read operation or a verify read operation, a reference cell including a reference resistance circuit configured to have different resistance values depending on the control signal, and a sense amplifier configured to sense a difference between a read voltage value applied from the memory cell and a reference voltage value applied from the reference resistance circuit may be provided.

公开(公告)号：US20240062795A1

公开(公告)日：2024-02-22

申请号：US18329215

申请日：2023-06-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daeshik KIM

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1675

Abstract: Disclosed is a memory device which includes a memory cell array that includes a plurality of memory cells and divided into a first region and a second region, and a sensing circuit that generates a first read current for determining data stored in memory cells belonging to the first region from among the plurality of memory cells wherein the second region configured to store a value of the first read current determined based on a value of a reference resistance for distinguishing a parallel state and an anti-parallel state of a memory cell where the data is stored and a value of an initial read current applied to the memory cell.

公开(公告)号：US20240119983A1

公开(公告)日：2024-04-11

申请号：US18545626

申请日：2023-12-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daeshik KIM

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1673 ,  G11C11/1697

Abstract: Disclosed is a memory device including a magnetic memory element. The memory device includes a memory cell array including a first region and a second region, the second region configured to store a value of a write voltage, the write voltage based on a value of a reference resistor for determining whether a programmed memory cell is in a parallel state or anti-parallel state, a voltage generator configured to generate a code value based on the value of the write voltage, and a write driver configured to drive a write current based on the code value, the write current being a current for storing data in the first region.

公开(公告)号：US20150123282A1

公开(公告)日：2015-05-07

申请号：US14460692

申请日：2014-08-15

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： Daeshik KIM

IPC: H01L27/22 ,  H01L23/535

CPC classification number: H01L23/535 ,  H01L27/228 ,  H01L43/08 ,  H01L43/12 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes an interlayer dielectric on a semiconductor substrate, a contact plug penetrating the interlayer dielectric, a pillar pattern disposed on the interlayer dielectric and having a central axis laterally offset from a central axis of the contact plug, a pad extending on the contact plug and along a sidewall of the pillar pattern, the pad being electrically connected to the contact plug, and a data storage portion on the pillar pattern and electrically connected to the pad.

Abstract translation: 半导体器件包括在半导体衬底上的层间电介质，穿透层间电介质的接触插塞，设置在层间电介质上的柱状图案，并且具有从接触插塞的中心轴线横向偏移的中心轴， 插塞并且沿着柱状图案的侧壁，所述垫电连接到所述接触插塞，以及所述柱状图案上的数据存储部分，并且电连接到所述垫。

公开(公告)号：US20250063739A1

公开(公告)日：2025-02-20

申请号：US18425147

申请日：2024-01-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kilho LEE ,  Daeshik KIM

IPC: H10B61/00

Abstract: A semiconductor device may include a substrate, data storage patterns on the substrate and spaced apart from each other in a first direction and a second direction that intersect each other and are parallel to a top surface of the substrate, first cell conductive lines that extend in the first direction and are spaced apart from each other in the second direction on the data storage patterns, cell via contacts that are spaced apart from each other in the first direction and disposed between a pair of the first cell conductive lines, dummy data storage patterns that are spaced apart from each other in the first direction between the first cell conductive lines and are disposed between the cell via contacts, and upper conductive lines on the cell via contacts and electrically connected to the cell via contacts, respectively.

公开(公告)号：US20220328085A1

公开(公告)日：2022-10-13

申请号：US17709784

申请日：2022-03-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daeshik KIM

IPC: G11C11/16 ,  G11C17/16

Abstract: Disclosed is a memory device including a magnetic storage element. The memory device includes a memory cell array, a voltage generator, and a write driver. The memory cell array includes a first region and a second region. The memory device is configured to store a value of a first read current determined based on a value of a reference resistance for distinguishing a parallel state and an anti-parallel state of a programmed memory cell. The sensing circuit is configured to generate the first read current based on the value of the first read current and to perform a read operation on the first region based on the first read current.

公开(公告)号：US20180137913A1

公开(公告)日：2018-05-17

申请号：US15612040

申请日：2017-06-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daeshik KIM

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C13/0028 ,  G11C13/0069 ,  G11C2013/0042 ,  G11C2013/0045 ,  G11C2013/0054 ,  G11C2213/79 ,  G11C2213/82

Abstract: A nonvolatile memory device includes: first memory cells connected to a first source line and a first bit line; second memory cells connected to a second source line and a second bit line; and a sense amplifier circuit connected to the first and second source lines and the first and second bit lines. The sense amplifier circuit includes: a first sense amplifier configured to apply a first read voltage to the first bit line and output a first amount of current of a selected first memory cell; a second sense amplifier configured to apply a second read voltage to the second bit line and output a second amount of current of a selected second memory cell; and a comparator configured to compare the first amount of current with the second amount of current to identify data of the selected first memory cell.