Method and apparatus for second order intercept point (IP2) calibration

    公开(公告)号:US10775512B2

    公开(公告)日:2020-09-15

    申请号:US16429742

    申请日:2019-06-03

    Abstract: An electronic device, a method, and a chipset for receiving global navigation satellite system (GNSS) signals are provided. The electronic device includes a processor configured to: downconvert, by an input/output (I/O) mixer including a first multiplier and a second multiplier, a modulated radio frequency wave to an intermediate frequency, where the modulated radio frequency wave is input to first inputs of the first multiplier and the second multiplier, and where an in-phase signal and a quadrature phase signal based on a square wave are input to second inputs of the first multiplier and the second multiplier, respectively; filter the downconverted modulated radio frequency wave; and convert the filtered downconverted modulated radio frequency wave to a digital signal.

    Precise time tagging of events over an imprecese link

    公开(公告)号:US09929857B2

    公开(公告)日:2018-03-27

    申请号:US15005298

    申请日:2016-01-25

    Abstract: A system for precise timing and synchronization of events is provided. The system includes a first terminal including one or more first counters and a packetizer configured to create a packetized data stream having one or more event tags. The system also includes a second terminal that includes one or more second counters and a depacketizer. The second counter(s) is/are configured to count clock pulses generated by a first clock of the first terminal at a first clock rate. The depacketizer is configured to receive the packetized data stream and detect the event tag(s). When the at least one event tag is detected, the second terminal calculates a time at which the first terminal created the packetized data stream based on a count value of the second counter(s) and a count value of the first counter(s) of the first terminal.

    DIGITAL REAL TIME CLOCK MONITOR FOR A GNSS RECEIVER AND SINGLE PIN SIGNALLING FOR POWER-ON RESET AND WAKE-UP INTERRUPT
    4.
    发明申请
    DIGITAL REAL TIME CLOCK MONITOR FOR A GNSS RECEIVER AND SINGLE PIN SIGNALLING FOR POWER-ON RESET AND WAKE-UP INTERRUPT 有权
    用于GNSS接收机的数字实时时钟监视器和用于上电复位和唤醒中断的单PIN信号

    公开(公告)号:US20150097726A1

    公开(公告)日:2015-04-09

    申请号:US14328143

    申请日:2014-07-10

    CPC classification number: G01S19/23 G01S19/235 G01S19/34

    Abstract: Methods, systems, and devices for monitoring a Real Time Clock (RTC) oscillator using Digital Signal Processing (DSP), where a resistance/capacitance (RC) oscillator is configured to output a digital pulse signal and a digital RTC Monitor Integrated Circuit (IC) is configured to monitor the RTC oscillator timing signal using the RC oscillator signal. In one aspect, the RTC Monitor IC includes an RTC input configured to receive the RTC oscillator timing signal; an RC input configured to receive the RC oscillator digital pulse signal; and an RTC reset output configured to output an RTC reset signal when a comparison of the RTC and RC oscillator inputs show the RTC oscillator has missed one or more clock cycles. A single wire input/output for both reset and interrupt signals between circuits is also described.

    Abstract translation: 用于使用数字信号处理(DSP)监视实时时钟(RTC)振荡器的方法,系统和设备,其中电阻/电容(RC)振荡器配置为输出数字脉冲信号和数字RTC监视器集成电路(IC) )配置为使用RC振荡器信号监视RTC振荡器定时信号。 在一个方面,RTC监视器IC包括被配置为接收RTC振荡器定时信号的RTC输入; RC输入配置为接收RC振荡器数字脉冲信号; 以及RTC复位输出,当RTC和RC振荡器输入的比较显示RTC振荡器已经错过一个或多个时钟周期时,配置为输出RTC复位信号。 还描述了用于电路之间的复位和中断信号的单线输入/输出。

    Method and apparatus for second order intercept point (IP2) calibration

    公开(公告)号:US11067702B2

    公开(公告)日:2021-07-20

    申请号:US17018370

    申请日:2020-09-11

    Abstract: An electronic device, a method, and a chipset for receiving global navigation satellite system (GNSS) signals are provided. An input/output (I/O) mixer including a first multiplier and a second multiplier downconverts a modulated radio frequency wave to an intermediate frequency. The modulated radio frequency wave is input to first inputs of the first multiplier and the second multiplier, and where an in-phase signal, from a first digital to analog converter (DAC), and a quadrature phase signal, from a second DAC, are input to second inputs of the first multiplier and the second multiplier, respectively. A mixer imbalance between the first mixer and the second mixer is reduced using direct current (DC) bias voltages from the first DAC and the second DAC. The DC bias voltages are determined based on a first and second DAC codes of the first and second DACs. The downconverted modulated radio frequency wave is filtered.

    System and method for modeling and correcting frequency of quartz crystal oscillator

    公开(公告)号:US10914643B2

    公开(公告)日:2021-02-09

    申请号:US16884620

    申请日:2020-05-27

    Abstract: A method and system for generating a crystal model for a test product including a crystal oscillator are herein disclosed. The method includes measuring a first temperature of the test product and measuring a first frequency error of the crystal oscillator at a first calibration point during a product testing process, measuring a second temperature of the test product and measuring a second frequency error of the crystal oscillator at a second calibration point during the product testing process, estimating two parameters from the first temperature, first frequency error, second temperature, and second frequency error, and determining a 3rd order polynomial for the crystal model based on the two parameters.

    System and method for modeling and correcting frequency of quartz crystal oscillator

    公开(公告)号:US10823623B2

    公开(公告)日:2020-11-03

    申请号:US16161985

    申请日:2018-10-16

    Abstract: A method and system for generating a crystal model for a test product including a crystal oscillator are herein disclosed. The method includes measuring a first temperature of the test product and measuring a first frequency error of the crystal oscillator at a first calibration point during a product testing process, measuring a second temperature of the test product and measuring a second frequency error of the crystal oscillator at a second calibration point during the product testing process, estimating two parameters from the first temperature, first frequency error, second temperature, and second frequency error, and determining a 3rd order polynomial for the crystal model based on the two parameters.

    Precise time tagging of events over an imprecise link
    10.
    发明授权
    Precise time tagging of events over an imprecise link 有权
    通过不精确的链接精确地标记事件

    公开(公告)号:US09277515B2

    公开(公告)日:2016-03-01

    申请号:US14335437

    申请日:2014-07-18

    Abstract: A system for precise timing and synchronization of events is provided. The system includes a first terminal including one or more first counters and a packetizer configured to create a packetized data stream having one or more event tags. The system also includes a second terminal that includes one or more second counters and a depacketizer. The second counter(s) is/are configured to count clock pulses generated by a first clock of the first terminal at a first clock rate. The depacketizer is configured to receive the packetized data stream and detect the event tag(s). When the at least one event tag is detected, the second terminal calculates a time at which the first terminal created the packetized data stream based on a count value of the second counter(s) and a count value of the first counter(s) of the first terminal.

    Abstract translation: 提供了一种精确定时和事件同步的系统。 该系统包括包括一个或多个第一计数器的第一终端和被配置为创建具有一个或多个事件标签的分组化数据流的分组器。 该系统还包括第二终端,其包括一个或多个第二计数器和解封装器。 第二计数器被配置为以第一时钟速率对由第一终端的第一时钟产生的时钟脉冲进行计数。 解包器被配置为接收分组数据流并检测事件标签。 当检测到至少一个事件标签时,第二终端基于第二计数器的计数值和第一计数器的计数值来计算第一终端创建分组化数据流的时间 第一个终端。

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