公开(公告)号：US20190122995A1

公开(公告)日：2019-04-25

申请号：US16052117

申请日：2018-08-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Han Ko ,  Bo Ram Kang ,  Dong Kwan Kim

IPC: H01L23/552 ,  H01L23/31 ,  H01L23/29 ,  H01L25/065 ,  H01L25/00 ,  H01L21/56

Abstract: A semiconductor package can include a substrate and a semiconductor chip on the substrate. A first molding portion can cover the semiconductor chip and can include a first sidewall and a second sidewall opposite each other. A second molding portion can extend on the substrate along the first sidewall and along the second sidewall, where the first molding portion can include a nonconductive material, and the second molding portion can include a conductive material.

公开(公告)号：US10896879B2

公开(公告)日：2021-01-19

申请号：US16201708

申请日：2018-11-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kun Sil Lee ,  Dong Kwan Kim ,  Bo Ram Kang ,  Ho Geon Song ,  Won Keun Kim

IPC: H01L23/552 ,  G01N23/18

Abstract: A semiconductor package includes a semiconductor package substrate. An insulating layer is disposed on the semiconductor package substrate. A semiconductor chip is disposed on the semiconductor package substrate and is covered by the insulating layer. A reflective layer is disposed on the insulating layer and is spaced apart from the semiconductor chip. The reflective layer is configured to selectively transmit radiation through to the insulating layer. A protective layer is disposed on the reflective layer.

公开(公告)号：US12027495B2

公开(公告)日：2024-07-02

申请号：US17316044

申请日：2021-05-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kun Sil Lee ,  Dong Kwan Kim

IPC: H01L25/065 ,  H01L21/56 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L25/00 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L21/565 ,  H01L21/76804 ,  H01L21/76819 ,  H01L21/76849 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53223 ,  H01L25/50 ,  H01L21/7685 ,  H01L23/315 ,  H01L24/81 ,  H01L2221/101 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2225/06548

Abstract: A method of manufacturing a semiconductor package includes forming a first redistribution structure, forming a plurality of conductive pillars on the first redistribution structure, mounting the first semiconductor chip on the first redistribution structure, forming an encapsulant configured to cover an upper surface of the first redistribution structure, the plurality of conductive pillars, and the first semiconductor chip, planarizing the encapsulant, exposing the plurality of conductive pillars by forming an opening in the planarized encapsulant, and forming a second redistribution structure connected to the plurality of conductive pillars on the first semiconductor chip and the encapsulant. Upper surfaces of the plurality of conductive pillars are located at a lower level than the upper surface of the first semiconductor chip, and an upper surface of a connection via included in the second redistribution structure has a width greater than a width of a lower surface of the connection via.

公开(公告)号：US11894403B2

公开(公告)日：2024-02-06

申请号：US17239650

申请日：2021-04-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong Kwan Kim

IPC: H01L27/146 ,  C08K3/36 ,  C08K3/22

CPC classification number: H01L27/14618 ,  C08K3/22 ,  C08K3/36 ,  H01L27/1463 ,  H01L27/1464 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/14683 ,  C08K2003/2227

Abstract: A semiconductor package including a semiconductor chip on a package substrate, a transparent substrate on the semiconductor chip, an attachment dam between the semiconductor chip and the transparent substrate, the attachment dam extending along an edge of the semiconductor chip, a first molding layer on the package substrate and surrounding a side surface of the semiconductor chip and including a first epoxy resin, and a second molding layer on the package substrate and filling a space between the semiconductor chip and the first molding layer and including a second epoxy resin. The first epoxy resin includes a first filler containing at least one of silica or alumina. The second epoxy resin includes a second filler containing at least one of silica or alumina. The content of the second filler in the second epoxy resin is greater than a content of the first filler in the first epoxy resin.

公开(公告)号：US11031375B2

公开(公告)日：2021-06-08

申请号：US16415058

申请日：2019-05-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kun Sil Lee ,  Dong Kwan Kim

IPC: H01L25/065 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L23/528 ,  H01L25/00 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: A method of manufacturing a semiconductor package includes forming a first redistribution structure, forming a plurality of conductive pillars on the first redistribution structure, mounting the first semiconductor chip on the first redistribution structure, forming an encapsulant configured to cover an upper surface of the first redistribution structure, the plurality of conductive pillars, and the first semiconductor chip, planarizing the encapsulant, exposing the plurality of conductive pillars by forming an opening in the planarized encapsulant, and forming a second redistribution structure connected to the plurality of conductive pillars on the first semiconductor chip and the encapsulant. Upper surfaces of the plurality of conductive pillars are located at a lower level than the upper surface of the first semiconductor chip, and an upper surface of a connection via included in the second redistribution structure has a width greater than a width of a lower surface of the connection via.