公开(公告)号：US20220068718A1

公开(公告)日：2022-03-03

申请号：US17523223

申请日：2021-11-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Min KIM ,  Sunhom Steve PAAK ,  Heon-Jong SHIN ,  Dong-Ho CHA

IPC: H01L21/8234

Abstract: Semiconductor devices and methods of forming the semiconductor devices are provided. The methods may include forming a fin, forming a first device isolating layer on a side of the fin, forming a second device isolating layer extending through the first device isolating layer, forming first and second gates traversing the fin and forming a third device isolating layer between the first and second gates. The first device isolating layer may include a first material and a lowermost surface at a first depth. The second device isolating layer may include a second material and a lowermost surface at a second depth greater than the first depth. The third device isolating layer may extend into the fin, may include a lowermost surface at a third depth less than the first depth and a third material different from the first and the second materials.

公开(公告)号：US20220301939A1

公开(公告)日：2022-09-22

申请号：US17830396

申请日：2022-06-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Min KIM ,  Sunhom Steve PAAK ,  Heon-Jong SHIN ,  Dong-Ho CHA

IPC: H01L21/8234

Abstract: Semiconductor devices and methods of forming the semiconductor devices are provided. The methods may include forming a fin, forming a first device isolating layer on a side of the fin, forming a second device isolating layer extending through the first device isolating layer, forming first and second gates traversing the fin and forming a third device isolating layer between the first and second gates. The first device isolating layer may include a first material and a lowermost surface at a first depth. The second device isolating layer may include a second material and a lowermost surface at a second depth greater than the first depth. The third device isolating layer may extend into the fin, may include a lowermost surface at a third depth less than the first depth and a third material different from the first and the second materials.

公开(公告)号：US20170018464A1

公开(公告)日：2017-01-19

申请号：US15211200

申请日：2016-07-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Min KIM ,  Ji-Su KANG ,  Byung-Chan RYU ,  Jae-Hyun PARK ,  Yu-Ri LEE ,  Dong-Ho CHA

IPC: H01L21/8238 ,  H01L29/08 ,  H01L29/161 ,  H01L23/532 ,  H01L29/165 ,  H01L27/092 ,  H01L23/535 ,  H01L29/78 ,  H01L29/16

CPC classification number: H01L21/823871 ,  H01L21/76897 ,  H01L21/823814 ,  H01L21/823821 ,  H01L23/485 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/665 ,  H01L29/7848 ,  H01L2029/7858

Abstract: A semiconductor device includes a first fin-type pattern and a second fin-type pattern which protrude upwardly from an upper surface of a field insulating film and extend in a first direction. A gate structure intersects the first fin-type pattern and the second fin-type pattern. A first epitaxial layer is on the first fin-type pattern on at least one side of the gate structure, and a second epitaxial layer is on the second fin-type pattern on at least one side of the gate structure. A metal contact covers outer circumferential surfaces of the first epitaxial layer and the second epitaxial layer. The first epitaxial layer contacts the second epitaxial layer.

Abstract translation: 半导体器件包括从场绝缘膜的上表面向上突出并沿第一方向延伸的第一鳍式图案和第二鳍片型图案。 栅极结构与第一鳍状图案和第二鳍片图案相交。 第一外延层位于栅极结构的至少一侧的第一鳍式图案上，第二外延层位于栅极结构的至少一侧上的第二鳍型图案上。 金属接触覆盖第一外延层和第二外延层的外圆周表面。 第一外延层接触第二外延层。

公开(公告)号：US20160079125A1

公开(公告)日：2016-03-17

申请号：US14812137

申请日：2015-07-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Min KIM ,  Cheol KIM ,  Dong-Ho CHA

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/306 ,  H01L21/311

CPC classification number: H01L21/823431 ,  H01L21/823437 ,  H01L21/823481

Abstract: In a method of manufacturing a semiconductor device, a substrate is etched to form active fins spaced apart from one another in a first direction, and each active fin extends in the first direction. An isolation pattern is formed on the substrate to partially fill a space between the active fins. A mold pattern is formed on the isolation pattern, the mold pattern covering at least a portion of each of the active fins and including an opening exposing a portion of the isolation pattern between the active fins in the first direction. An insulation pattern is formed to fill the opening. The mold pattern is removed to expose the active fins. A gate structure and a dummy structure are formed on the exposed active fins and the insulation pattern, respectively, the gate structure and the dummy structure extending in a second direction substantially perpendicular to the first direction.

Abstract translation: 在制造半导体器件的方法中，蚀刻衬底以形成在第一方向上彼此间隔开的有效散热片，并且每个活动鳍片沿第一方向延伸。 在衬底上形成隔离图案，以部分填充活性鳍片之间的空间。 在隔离图案上形成模具图案，模具图案覆盖每个活动翅片的至少一部分，并且包括在第一方向上暴露活动翅片之间的隔离图案的一部分的开口。 形成绝缘图案以填充开口。 去除模具图案以暴露活性散热片。 分别在暴露的活性鳍片和绝缘图案上形成栅极结构和虚拟结构，栅极结构和虚拟结构在基本上垂直于第一方向的第二方向上延伸。

公开(公告)号：US20200227321A1

公开(公告)日：2020-07-16

申请号：US16833885

申请日：2020-03-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Min KIM ,  Sunhom Steve PAAK ,  Heon-Jong SHIN ,  Dong-Ho CHA

IPC: H01L21/8234

Abstract: Semiconductor devices and methods of forming the semiconductor devices are provided. The methods may include forming a fin, forming a first device isolating layer on a side of the fin, forming a second device isolating layer extending through the first device isolating layer, forming first and second gates traversing the fin and forming a third device isolating layer between the first and second gates. The first device isolating layer may include a first material and a lowermost surface at a first depth. The second device isolating layer may include a second material and a lowermost surface at a second depth greater than the first depth. The third device isolating layer may extend into the fin, may include a lowermost surface at a third depth less than the first depth and a third material different from the first and the second materials.

公开(公告)号：US20180190543A1

公开(公告)日：2018-07-05

申请号：US15903718

申请日：2018-02-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Min KIM ,  Sunhom Steve PAAK ,  Heon-Jong SHIN ,  Dong-Ho CHA

IPC: H01L21/8234

CPC classification number: H01L21/823431 ,  H01L21/823481

Abstract: Semiconductor devices and methods of forming the semiconductor devices are provided. The methods may include forming a fin, forming a first device isolating layer on a side of the fin, forming a second device isolating layer extending through the first device isolating layer, forming first and second gates traversing the fin and forming a third device isolating layer between the first and second gates. The first device isolating layer may include a first material and a lowermost surface at a first depth. The second device isolating layer may include a second material and a lowermost surface at a second depth greater than the first depth. The third device isolating layer may extend into the fin, may include a lowermost surface at a third depth less than the first depth and a third material different from the first and the second materials.