公开(公告)号：US20190013401A1

公开(公告)日：2019-01-10

申请号：US16128152

申请日：2018-09-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Min KIM ,  Kyung-Seok OH ,  Cheol KIM ,  Heon-Jong SHIN ,  Jong-Ryeol YOO ,  Hyun-Jung LEE ,  Seong-Hoon JEONG

IPC: H01L29/78 ,  H01L27/12 ,  H01L21/84 ,  H01L29/66

Abstract: Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes a lower fin that protrudes from a substrate and extends in a first direction, an oxide film the lower fin, an upper fin that protrudes from the oxide film and that is spaced apart from the lower fin at a position corresponding to the lower fin, and a gate structure the upper fin that extends in a second direction to intersect the upper fin, wherein germanium (Ge) is included in a portion of the oxide film located between the lower fin and the upper fin.

公开(公告)号：US20220301939A1

公开(公告)日：2022-09-22

申请号：US17830396

申请日：2022-06-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Min KIM ,  Sunhom Steve PAAK ,  Heon-Jong SHIN ,  Dong-Ho CHA

IPC: H01L21/8234

Abstract: Semiconductor devices and methods of forming the semiconductor devices are provided. The methods may include forming a fin, forming a first device isolating layer on a side of the fin, forming a second device isolating layer extending through the first device isolating layer, forming first and second gates traversing the fin and forming a third device isolating layer between the first and second gates. The first device isolating layer may include a first material and a lowermost surface at a first depth. The second device isolating layer may include a second material and a lowermost surface at a second depth greater than the first depth. The third device isolating layer may extend into the fin, may include a lowermost surface at a third depth less than the first depth and a third material different from the first and the second materials.

公开(公告)号：US20220068718A1

公开(公告)日：2022-03-03

申请号：US17523223

申请日：2021-11-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Min KIM ,  Sunhom Steve PAAK ,  Heon-Jong SHIN ,  Dong-Ho CHA

IPC: H01L21/8234

Abstract: Semiconductor devices and methods of forming the semiconductor devices are provided. The methods may include forming a fin, forming a first device isolating layer on a side of the fin, forming a second device isolating layer extending through the first device isolating layer, forming first and second gates traversing the fin and forming a third device isolating layer between the first and second gates. The first device isolating layer may include a first material and a lowermost surface at a first depth. The second device isolating layer may include a second material and a lowermost surface at a second depth greater than the first depth. The third device isolating layer may extend into the fin, may include a lowermost surface at a third depth less than the first depth and a third material different from the first and the second materials.

公开(公告)号：US20160049394A1

公开(公告)日：2016-02-18

申请号：US14629249

申请日：2015-02-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heon-Jong SHIN ,  Deok-Han BAE ,  Dae-Hee WEON ,  Hwi-Chan JUN

IPC: H01L27/088 ,  H01L29/417 ,  H01L23/532 ,  H01L29/45 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L27/0886 ,  H01L21/76804 ,  H01L21/76883 ,  H01L21/76895 ,  H01L21/823475 ,  H01L23/485 ,  H01L27/088 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/4236 ,  H01L29/45 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/78 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a transistor formed on a substrate and including a gate electrode and a source/drain, an interlayer insulating layer covering the transistor, a first contact hole formed in the interlayer insulating layer to expose a part of the transistor, a first barrier metal conformally formed on an inner surface of the first contact hole, a first conductive layer formed on the first barrier metal to fill the first contact hole, a second contact hole formed on the first conductive layer in the interlayer insulating layer and having a larger width than the first contact hole, a second barrier metal conformally formed on an inner surface of the second contact hole, and a second conductive layer formed on the second barrier metal to fill the second contact hole, wherein the second barrier metal is formed between the first conductive layer and the second conductive layer.

Abstract translation: 半导体器件包括形成在衬底上并包括栅极和源极/漏极的晶体管，覆盖晶体管的层间绝缘层，形成在层间绝缘层中以暴露晶体管的一部分的第一接触孔，第一栅极 在第一接触孔的内表面上保形地形成的金属，形成在第一阻挡金属上以填充第一接触孔的第一导电层，形成在层间绝缘层中的第一导电层上并具有较大宽度的第二接触孔 形成在第二接触孔的内表面上的第二阻挡金属和形成在第二阻挡金属上以填充第二接触孔的第二导电层，其中第二阻挡金属形成在第一接触孔之间， 导电层和第二导电层。

公开(公告)号：US20200227321A1

公开(公告)日：2020-07-16

申请号：US16833885

申请日：2020-03-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Min KIM ,  Sunhom Steve PAAK ,  Heon-Jong SHIN ,  Dong-Ho CHA

IPC: H01L21/8234

Abstract: Semiconductor devices and methods of forming the semiconductor devices are provided. The methods may include forming a fin, forming a first device isolating layer on a side of the fin, forming a second device isolating layer extending through the first device isolating layer, forming first and second gates traversing the fin and forming a third device isolating layer between the first and second gates. The first device isolating layer may include a first material and a lowermost surface at a first depth. The second device isolating layer may include a second material and a lowermost surface at a second depth greater than the first depth. The third device isolating layer may extend into the fin, may include a lowermost surface at a third depth less than the first depth and a third material different from the first and the second materials.

公开(公告)号：US20180190543A1

公开(公告)日：2018-07-05

申请号：US15903718

申请日：2018-02-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Min KIM ,  Sunhom Steve PAAK ,  Heon-Jong SHIN ,  Dong-Ho CHA

IPC: H01L21/8234

CPC classification number: H01L21/823431 ,  H01L21/823481

Abstract: Semiconductor devices and methods of forming the semiconductor devices are provided. The methods may include forming a fin, forming a first device isolating layer on a side of the fin, forming a second device isolating layer extending through the first device isolating layer, forming first and second gates traversing the fin and forming a third device isolating layer between the first and second gates. The first device isolating layer may include a first material and a lowermost surface at a first depth. The second device isolating layer may include a second material and a lowermost surface at a second depth greater than the first depth. The third device isolating layer may extend into the fin, may include a lowermost surface at a third depth less than the first depth and a third material different from the first and the second materials.