公开(公告)号：US12027401B2

公开(公告)日：2024-07-02

申请号：US17203036

申请日：2021-03-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gwanghee Jo ,  Dongjoo Moon ,  Siwoong Woo ,  Sunjung Kim ,  Donggil Shim ,  Huijae Kim ,  Seungdae Seok

IPC: H01L21/68 ,  G03F7/00 ,  H01L21/677 ,  H01L21/683

CPC classification number: H01L21/68 ,  G03F7/70775 ,  H01L21/67742 ,  H01L21/683 ,  H01L2224/75701 ,  H01L2224/75703

Abstract: A semiconductor substrate alignment device includes: a lower chuck; a lower chuck driving unit; an upper chuck above and overlapping the lower chuck; observation windows in the upper chuck, imaging units respectively configured to irradiate light through the observation windows and to obtain images by detecting light reflected from the semiconductor substrates; a distance sensor configured to detect a distance between an edge of the lower chuck and an edge of the upper chuck; and a control unit configured to identify first and second alignment keys from images of first and second semiconductor substrates, determine an alignment error value of the first and second semiconductor substrates, and compensate for the alignment error value by driving the lower chuck driving unit.

公开(公告)号：US09553069B2

公开(公告)日：2017-01-24

申请号：US14852825

申请日：2015-09-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ilyoung Han ,  Kyoungran Kim ,  Donggil Shim ,  Geunsik Oh ,  Youngjoo Lee ,  Junho Lee ,  Sukwon Lee

IPC: B23K37/04 ,  H01L23/00 ,  B23K3/08

CPC classification number: H01L24/75 ,  B23K3/087 ,  B23K37/04 ,  H01L2224/75252 ,  H01L2224/75704 ,  H01L2224/75705 ,  H01L2224/7598

Abstract: A bonding apparatus of substrate manufacturing equipment includes an upper stage, a lower stage facing the upper stage and which is configure and dedicated to support a processed substrate on which semiconductor chips are stacked (set), and an elevating mechanism for raising the lower stage relative to the upper stage to provide pressure for pressing the substrate and chips towards each other.

Abstract translation: 基板制造装置的接合装置包括上层，与上层相对的下层，其构造为专用于支撑半导体芯片堆叠的被处理基板（设置），以及用于升高下层相对的升降机构 以提供将基板和芯片彼此挤压的压力。