公开(公告)号：US20220199522A1

公开(公告)日：2022-06-23

申请号：US17373573

申请日：2021-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eui Bok LEE ,  Donggon YOO ,  Wandon KIM

IPC: H01L23/522 ,  H01L23/528 ,  H01L29/08 ,  H01L29/06

Abstract: A semiconductor device including transistors on a substrate, a first interlayer insulating layer on the transistors, a first lower interconnection line and a second lower interconnection line in an upper portion of the first interlayer insulating layer, a dielectric layer being selectively on a top surface of the first interlayer insulating layer except top surfaces of the first and second lower interconnection lines, an etch stop layer on the first and second lower interconnection lines and the dielectric layer, a second interlayer insulating layer on the etch stop layer, and an upper interconnection line in the second interlayer insulating layer may be provided.

公开(公告)号：US20210066289A1

公开(公告)日：2021-03-04

申请号：US16851476

申请日：2020-04-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunyoung NOH ,  Wandon KIM ,  Hyunbae LEE ,  Donggon YOO ,  Dong-Chan LIM

IPC: H01L27/088 ,  H01L23/528 ,  H01L23/532 ,  H01L21/8234 ,  H01L21/321 ,  H01L21/768 ,  H01L29/06

Abstract: A semiconductor device includes an interlayer dielectric layer on a substrate, a first connection line that fills a first trench of the interlayer dielectric layer, the first trench having a first width, and a second connection line that fills a second trench of the interlayer dielectric layer, the second trench having a second width greater than the first width, and the second connection line including a first metal layer that covers an inner sidewall of the second trench, a barrier layer that covers a bottom surface of the second trench, and a second metal layer on the first metal layer and the barrier layer, the first connection line and the first metal layer include a first metal, and the second metal layer includes a second metal different from the first metal.

公开(公告)号：US20220352156A1

公开(公告)日：2022-11-03

申请号：US17846177

申请日：2022-06-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunyoung NOH ,  Wandon KIM ,  Hyunbae LEE ,  Donggon YOO ,  Dong-Chan LIM

IPC: H01L27/088 ,  H01L23/528 ,  H01L23/532 ,  H01L29/06 ,  H01L21/321 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/535

Abstract: A semiconductor device includes an interlayer dielectric layer on a substrate, a first connection line that fills a first trench of the interlayer dielectric layer, the first trench having a first width, and a second connection line that fills a second trench of the interlayer dielectric layer, the second trench having a second width greater than the first width, and the second connection line including a first metal layer that covers an inner sidewall of the second trench, a barrier layer that covers a bottom surface of the second trench, and a second metal layer on the first metal layer and the barrier layer, the first connection line and the first metal layer include a first metal, and the second metal layer includes a second metal different from the first metal.

公开(公告)号：US20240421070A1

公开(公告)日：2024-12-19

申请号：US18409491

申请日：2024-01-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunjung LEE ,  Sanghoon AHN ,  Donggon YOO ,  Jangeun LEE ,  Jeongwon HWANG

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: Disclosed are semiconductor devices and their fabrication methods. The semiconductor device comprises a substrate including an active pattern; a channel pattern on the active pattern; a source/drain pattern electrically connected to the channel pattern; a gate electrode on the channel pattern; an interlayer dielectric layer on the gate electrode, wherein the interlayer dielectric layer includes a recess; a via in the recess; a wiring line on the interlayer dielectric layer and electrically connected to the via; and an adhesion layer between the wiring line and an upper surface of the interlayer dielectric layer, wherein an upper surface of the via is closer than the upper surface of the interlayer dielectric layer to the substrate in a first direction, wherein the first direction is perpendicular to an upper surface of the substrate and wherein a portion of the adhesion layer is on a portion of an inner sidewall of the recess.

公开(公告)号：US20240321888A1

公开(公告)日：2024-09-26

申请号：US18493241

申请日：2023-10-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donggon YOO

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L23/528 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L27/0922 ,  H01L21/8221 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/5286 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: A semiconductor device may include: insulating patterns; a device isolation layer on side surfaces of the insulating patterns; gate structures; source/drain regions on the insulating patterns; a via structure between the gate structures and between the source/drain regions; and contact structures connected to the source/drain regions and the via structure, wherein the source/drain regions may include first source/drain regions and second source/drain, wherein the via structure may extend from the same level as lower surfaces of the first source/drain regions to the same level as upper surfaces of the second source/drain regions, and the via structure may include a portion in which a width of the via structure increases and then decreases or decreases and then increases, wherein the contact structures may include a first contact structure contacting the first source/drain regions and a second contact structure contacting the second source/drain regions.