公开(公告)号：US20230335606A1

公开(公告)日：2023-10-19

申请号：US18079057

申请日：2022-12-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonhyuk Lee ,  Sangduk Park ,  Dongsoo Seo ,  Hongsik Shin ,  Jinwook Lee

IPC: H01L29/417 ,  H01L29/40 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L29/41775 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/7851 ,  H01L29/66795 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/41733 ,  H01L29/775 ,  H01L29/66439

Abstract: A semiconductor device includes a gate structure on a substrate, a gate spacer on a sidewall of the gate structure, a source/drain layer on a portion of the substrate adjacent to the gate structure, and a first contact plug on the source/drain layer and contacting an outer sidewall of the gate spacer. The gate structure includes a first conductive pattern having a lower portion and an upper portion on the lower portion with a width greater than the lower portion and in contact with an inner sidewall of the gate spacer, a second conductive pattern on a lower surface and a sidewall of the lower portion of the first conductive pattern, and a gate insulating pattern on a lower surface and an outer sidewall of the second conductive pattern. An upper surface of the first conductive pattern is substantially coplanar with an upper surface of the first contact plug.