公开(公告)号：US20230335606A1

公开(公告)日：2023-10-19

申请号：US18079057

申请日：2022-12-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonhyuk Lee ,  Sangduk Park ,  Dongsoo Seo ,  Hongsik Shin ,  Jinwook Lee

IPC: H01L29/417 ,  H01L29/40 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L29/41775 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/7851 ,  H01L29/66795 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/41733 ,  H01L29/775 ,  H01L29/66439

Abstract: A semiconductor device includes a gate structure on a substrate, a gate spacer on a sidewall of the gate structure, a source/drain layer on a portion of the substrate adjacent to the gate structure, and a first contact plug on the source/drain layer and contacting an outer sidewall of the gate spacer. The gate structure includes a first conductive pattern having a lower portion and an upper portion on the lower portion with a width greater than the lower portion and in contact with an inner sidewall of the gate spacer, a second conductive pattern on a lower surface and a sidewall of the lower portion of the first conductive pattern, and a gate insulating pattern on a lower surface and an outer sidewall of the second conductive pattern. An upper surface of the first conductive pattern is substantially coplanar with an upper surface of the first contact plug.

公开(公告)号：US10205020B2

公开(公告)日：2019-02-12

申请号：US15348586

申请日：2016-11-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongseok Lee ,  Jeongyun Lee ,  Gigwan Park ,  Keo Myoung Shin ,  Hyunji Kim ,  Sangduk Park

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L21/8238 ,  H01L49/02 ,  H01L29/165

Abstract: A semiconductor device includes an active pattern having sidewalls defined by a device isolation pattern disposed on a substrate and an upper portion protruding from a top surface of the device isolation pattern, a liner insulating layer on the sidewalls of the active pattern, a gate structure on the active pattern, and source/drain regions at both sides of the gate structure. The liner insulating layer includes a first liner insulating layer and a second liner insulating layer having a top surface higher than a top surface of the first liner insulating layer. Each of the source/drain regions includes a first portion defined by the second liner insulating layer, and a second portion protruding upward from the second liner insulating layer and covering the top surface of the first liner insulating layer.

公开(公告)号：US11211294B2

公开(公告)日：2021-12-28

申请号：US16503728

申请日：2019-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonhyuk Lee ,  Jeongyun Lee ,  Yongseok Lee ,  Bosoon Kim ,  Sangduk Park ,  Seungchul Oh ,  Youngmook Oh

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/762 ,  H01L29/08 ,  H01L21/8238

Abstract: A semiconductor device includes a device isolation layer provided on a substrate, the device isolation layer defining first and second sub-active patterns, first and second gate electrodes crossing the first and second sub-active patterns, respectively, and an isolation structure provided on the device isolation layer between the first and second sub-active patterns. The first and second sub-active patterns extend in a first direction and are spaced apart from each other in the first direction. The device isolation layer includes a diffusion break region disposed between the first and second sub-active patterns. The isolation structure covers a top surface of the diffusion break region.

公开(公告)号：US20250142952A1

公开(公告)日：2025-05-01

申请号：US18796895

申请日：2024-08-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Haegeon JUNG ,  Dongkwon Kim ,  Myeongji Kim ,  Sangduk Park ,  Keunhee Bai ,  Gahyun Lim

IPC: H01L27/092 ,  H01L21/8238 ,  H01L23/528 ,  H01L25/18 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A method of manufacturing an integrated circuit device is provided. The method includes: providing a substrate including a base substrate layer, an insulating substrate layer, and a cover substrate layer that are sequentially stacked in a vertical direction; forming, on the substrate, a stacked structure including a plurality of sacrificial semiconductor layers and a plurality of nanosheet semiconductor layers that are alternately stacked one layer at a time; and forming a plurality of trench regions to define a plurality of fin-type active regions by etching the stacked structure and the substrate. The he forming of the plurality of trench regions includes, by using the insulating substrate layer as an etch stop layer, etching portions of the stacked structure and the cover substrate layer in the vertical direction up to an upper surface of the insulating substrate layer.

公开(公告)号：US11869811B2

公开(公告)日：2024-01-09

申请号：US17562802

申请日：2021-12-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonhyuk Lee ,  Jeongyun Lee ,  Yongseok Lee ,  Bosoon Kim ,  Sangduk Park ,  Seungchul Oh ,  Youngmook Oh

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/762 ,  H01L29/08 ,  H01L21/8238

CPC classification number: H01L21/823481 ,  H01L21/76224 ,  H01L21/823418 ,  H01L27/088 ,  H01L29/0847 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823814 ,  H01L27/0886

Abstract: A semiconductor device includes a device isolation layer provided on a substrate, the device isolation layer defining first and second sub-active patterns, first and second gate electrodes crossing the first and second sub-active patterns, respectively, and an isolation structure provided on the device isolation layer between the first and second sub-active patterns. The first and second sub-active patterns extend in a first direction and are spaced apart from each other in the first direction. The device isolation layer includes a diffusion break region disposed between the first and second sub-active patterns. The isolation structure covers a top surface of the diffusion break region.

公开(公告)号：US10366927B2

公开(公告)日：2019-07-30

申请号：US15405420

申请日：2017-01-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonhyuk Lee ,  Jeongyun Lee ,  Yongseok Lee ,  Bosoon Kim ,  Sangduk Park ,  Seungchul Oh ,  Youngmook Oh

IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/762 ,  H01L29/08 ,  H01L27/088 ,  H01L21/8238

Abstract: A semiconductor device includes a device isolation layer provided on a substrate, the device isolation layer defining first and second sub-active patterns, first and second gate electrodes crossing the first and second sub-active patterns, respectively, and an isolation structure provided on the device isolation layer between the first and second sub-active patterns. The first and second sub-active patterns extend in a first direction and are spaced apart from each other in the first direction. The device isolation layer includes a diffusion break region disposed between the first and second sub-active patterns. The isolation structure covers a top surface of the diffusion break region.