公开(公告)号：US11537360B2

公开(公告)日：2022-12-27

申请号：US17047377

申请日：2019-04-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongho Jang ,  Wooup Kwon ,  Dongyeop Kim ,  Jihyun Kim ,  Gajin Song ,  Yongjoon Jeon

IPC: G10L15/22 ,  G06F3/16 ,  H04L51/18 ,  H04L51/234

Abstract: Disclosed is a system. A system according to an embodiment includes: a first electronic device which includes a wireless communication circuit, a microphone, and a speaker, at least one processor which is a part of the first electronic device or remotely communicates with the electronic device; and at least one memory which resides on the first electronic device or on the outside of the first electronic device while operatively connected with the at least one processor, wherein the memory can store instructions which, when executed, cause the processor to: receive through the microphone a voice input including a request for performing a task that uses the first electronic device and is related to the transmission of data to a second external device; extract at least one parameter from the voice input; perform the task by using the wireless communication circuit; and transmit at least a portion of the at least one parameter to the second external device. Other embodiments understood through the present specification are also passible.

公开(公告)号：US09618983B2

公开(公告)日：2017-04-11

申请号：US14625837

申请日：2015-02-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongyeop Kim ,  Jaejun Lee

IPC: G06F1/16 ,  G06F1/18

CPC classification number: G06F1/18 ,  G06F1/189 ,  G11C5/04 ,  G11C5/063 ,  G11C5/14 ,  H01L23/50 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1064 ,  H01L2225/107 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/14511 ,  H01L2924/15313 ,  H05K1/0253 ,  H05K1/117 ,  H05K3/366

Abstract: A memory module includes a signal tab and a power tab spaced apart from each other on a surface layer of a substrate, the signal tab and the power tab defining a module tab area, a reference plane layer below the surface layer, the reference plane layer being recessed below the signal tab and being non-recessed below the power tab, and an insulating layer between the surface layer and the reference plane layer.

公开(公告)号：US11956890B2

公开(公告)日：2024-04-09

申请号：US17720364

申请日：2022-04-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yunho Lee ,  Yoojeong Kwon ,  Kyoungsun Kim ,  Dongyeop Kim ,  Sungjoo Park

IPC: H05K1/02 ,  H01P3/08 ,  H05K1/11 ,  H05K1/18 ,  G11C11/401 ,  G11C16/04

CPC classification number: H05K1/0245 ,  H01P3/088 ,  H05K1/115 ,  H05K1/181 ,  G11C11/401 ,  G11C16/0483 ,  H05K2201/10159

Abstract: A circuit board includes a first insulating layer; a first wiring pattern and a second wiring pattern each formed to be side to side with each other on an upper surface of the first insulating layer; a second insulating layer formed on the upper surface of the first insulating layer to cover the first and second wiring patterns; a third wiring pattern formed on an upper surface of the second insulating layer to overlap the first wiring pattern in a vertical direction; a fourth wiring pattern formed on the upper surface of the second insulating layer to overlap the second wiring pattern in the vertical direction; a first via passing through the second insulating layer and connecting the first and fourth wiring patterns; and a second via passing through the second insulating layer and connecting the second and third wiring patterns.

公开(公告)号：US11810852B2

公开(公告)日：2023-11-07

申请号：US17707267

申请日：2022-03-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daae Huh ,  Dongyeop Kim

IPC: H01L23/522 ,  H01L23/64 ,  H01L25/18 ,  H05K1/16

CPC classification number: H01L23/5223

Abstract: A substrate for semiconductor module includes a plurality of insulating layers sequentially stacked on one another, N signal lines transmitting N signals respectively, the N signal lines having N vias that at least partially penetrate through the plurality of insulating layers and are arranged in an N-sided polygon shape in a plan view, and a capacitor element configured to provide capacitive coupling between the N signal lines, the capacitor element having a first coupling element that provides capacitive coupling between first and second vias adjacent to each other among the N vias and a second coupling element that provides capacitive coupling between third and fourth vias that are not adjacent to each other among the N vias.