公开(公告)号：US11380386B2

公开(公告)日：2022-07-05

申请号：US17147557

申请日：2021-01-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soo-Woong Lee ,  Doo-Ho Cho ,  Sang Soo Park ,  Yongkyu Lee

IPC: G11C16/12 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4093 ,  G11C16/04 ,  G11C16/34 ,  G11C16/32 ,  G11C16/28

Abstract: Disclosed is a nonvolatile memory device, which includes a memory cell array that includes a plurality of memory cells, a page buffer circuit that is connected with the memory cell array through a plurality of bit lines and performs a sensing operation of sensing memory cells selected from the plurality of memory cells through the plurality of bit lines during a sensing time, an input/output circuit that performs a data output operation of outputting data from the page buffer circuit to an external device through data lines, and a sensing time control circuit that adjusts the sensing time when the data output operation is performed during the sensing time.

公开(公告)号：US08804422B2

公开(公告)日：2014-08-12

申请号：US13767166

申请日：2013-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Ho Chung ,  Sang-Soo Park ,  Ji-Suk Kim ,  Doo-Ho Cho

IPC: G11C11/34 ,  G11C16/10 ,  G11C16/34 ,  G11C16/04

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2213/71

Abstract: A method of programming selected memory cells to a plurality of target states comprises applying a first verification voltage to the selected memory cells to perform a verification read operation on memory cells programmed to at least one target state, applying a program voltage to the selected memory cells, and applying a second verification voltage lower than the first verification voltage to the selected memory cells to perform a verification read operation on memory cells programmed to the at least one target state, wherein the second verification voltage is provided in a specified program loop and subsequent program loops. The second verification voltage is set such that a number of slow bits in the at least one target state is different from the number of slow bits in another target state.

Abstract translation: 将选择的存储器单元编程为多个目标状态的方法包括将第一验证电压施加到所选择的存储器单元以对被编程为至少一个目标状态的存储器单元执行验证读取操作，将程序电压施加到所选择的存储器单元 并且将低于第一验证电压的第二验证电压施加到所选择的存储器单元，以对被编程为至少一个目标状态的存储器单元执行验证读取操作，其中第二验证电压被提供在指定的程序循环中并且随后 程序循环。 第二验证电压被设置为使得至少一个目标状态中的慢比特数目与另一目标状态下的慢比特数不同。