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公开(公告)号：US10573386B2
公开(公告)日：2020-02-25
申请号：US16035958
申请日：2018-07-16
发明人： Wan-Dong Kim , Tae-Hyun Kim , Sang-Wan Nam , Sang-Soo Park , Jae-Yong Jeong
IPC分类号： G11C16/04 , G11C16/08 , G11C16/28 , G11C16/10 , G11C16/26 , G11C16/34 , G11C11/56 , G11C16/32 , G11C5/06
摘要： To operate a memory device including a plurality of NAND strings, an unselected NAND string among a plurality of NAND strings is floated when a voltage of a selected word line is increased such that a channel voltage of the unselected NAND string is boosted. The channel voltage of the unselected NAND string may be discharged when the voltage of the selected word line is decreased. The load when the voltage of the selected word line increases may be reduced by floating the unselected NAND string to boost the channel voltage of the unselected NAND string together with the increase of the voltage of the selected word line. The load when the voltage of the selected word line is decreased may be reduced by discharging the boosted channel voltage of the unselected NAND string when the voltage of the selected word line is decreased. Through such reduction of the load of the selected word line, a voltage setup time may be reduced and an operation speed of the memory device may be enhanced.
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公开(公告)号：US10147495B2
公开(公告)日：2018-12-04
申请号：US15664180
申请日：2017-07-31
发明人： Sang-Soo Park
摘要： A nonvolatile memory device includes a cell array comprising memory cells; a voltage generator that provides a program or verification voltage to a word line of memory cells selected from the memory cells; a page buffer that transfers write data to be programmed in the selected memory cells through bit lines and to sense whether the selected memory cells are programmed to target states, based on the verification voltage; and a control logic that controls the voltage generator such that the program voltage and the verification voltage are provided to the word line in units of multiple loops during a program operation, the control logic including a loop status circuit that detects values of state pass loops associated with the target states from a sensing result of the page buffer and determines whether the program operation is successful, based on the values of the state pass loops.
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公开(公告)号：US09672933B2
公开(公告)日：2017-06-06
申请号：US14733583
申请日：2015-06-08
发明人： Joon-Soo Kwon , Sang-Soo Park
CPC分类号： G11C16/3459 , G11C11/5628 , G11C11/5671 , G11C16/0483 , G11C16/10 , G11C2211/5621
摘要： A method of programming a memory device includes programming a low bit to a memory cell included in a word line and a bit line based on a first verification condition, the low bit belonging to a group of bits including a high bit. The first verification condition is based on at least one of a first bit line current, a first develop time for verifying the programming of the low bit, and a first word line voltage. The method includes programming the high bit to the memory cell based on a second verification condition. The second verification condition is based on at least one of a second bit line current, a second develop time for verifying the programming of the high bit, and a second word line voltage.
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4.发明授权公开(公告)号：US10528420B2
公开(公告)日：2020-01-07
申请号：US13935604
申请日：2013-07-05
发明人： Donghun Kwak , Sang-Soo Park , Jaewoo Im
IPC分类号： G06F11/10
摘要： A flash memory controller for a flash memory system includes an ECC circuit that receives first page data and second page data read from the flash memory, and respectively counts a first number of fail bits in the first page data and a second number of fail bits in the second page data, an abnormal wordline detector configured to compare the first number of fail bits and second number of fail bits to derive a fail bit change rate between the first page data and the second page data, and generate an abnormal wordline detection signal in response to the fail bit change rate, and a control unit that controls operation of the flash memory in response to the abnormal wordline detection signal.
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公开(公告)号：US09672149B2
公开(公告)日：2017-06-06
申请号：US14585286
申请日：2014-12-30
发明人： Sang-Soo Park
CPC分类号： G06F12/0246 , G06F12/0238 , G06F2212/1036 , G06F2212/7201 , G06F2212/7203 , G11C7/1006 , G11C16/12
摘要： In one embodiment of the inventive concept, a partial page program method is provided for a system comprising a nonvolatile memory device. The method comprises loading random data stored in the nonvolatile memory device into a page buffer circuit in the nonvolatile memory device, reloading partial page data having a size corresponding to a portion of one page into the page buffer circuit after the random data is loaded by receiving the partial page data from a memory controller, and programming, to a target page, page data stored in the page buffer circuit after the random data is loaded and the partial page data is reloaded.
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6.发明授权Nonvolatile memory device with flag cells and user device including the same 有权具有标志单元的非易失性存储器件和包括其的用户设备公开(公告)号：US08976592B2
公开(公告)日：2015-03-10
申请号：US13804128
申请日：2013-03-14
发明人： Sang-Soo Park , Kitae Park
CPC分类号： G11C16/28 , G11C11/5628 , G11C11/5642 , G11C16/3427 , G11C2211/5646
摘要： A nonvolatile memory device includes a flag cell configured to store flag information, a plurality of dummy cells adjacent to the flag cell, and program control logic configured to control a program operation on the flag cell and a dummy program operation on the plurality of dummy cells. When the program operation on the flag cell is performed, the program control logic performs the dummy program operation on at least one of the plurality of dummy cells.
摘要翻译： 非易失性存储器件包括：标志单元，被配置为存储标志信息，与标志单元相邻的多个虚设单元;以及程序控制逻辑，被配置为控制对所述标志单元的编程操作，以及对所述多个虚设单元进行虚拟程序操作 。 当执行对标志单元的编程操作时，程序控制逻辑对多个虚设单元中的至少一个执行虚拟程序操作。
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公开(公告)号：US08804422B2
公开(公告)日：2014-08-12
申请号：US13767166
申请日：2013-02-14
发明人： Ki Ho Chung , Sang-Soo Park , Ji-Suk Kim , Doo-Ho Cho
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/3459 , G11C2211/5621 , G11C2213/71
摘要： A method of programming selected memory cells to a plurality of target states comprises applying a first verification voltage to the selected memory cells to perform a verification read operation on memory cells programmed to at least one target state, applying a program voltage to the selected memory cells, and applying a second verification voltage lower than the first verification voltage to the selected memory cells to perform a verification read operation on memory cells programmed to the at least one target state, wherein the second verification voltage is provided in a specified program loop and subsequent program loops. The second verification voltage is set such that a number of slow bits in the at least one target state is different from the number of slow bits in another target state.
摘要翻译： 将选择的存储器单元编程为多个目标状态的方法包括将第一验证电压施加到所选择的存储器单元以对被编程为至少一个目标状态的存储器单元执行验证读取操作，将程序电压施加到所选择的存储器单元 并且将低于第一验证电压的第二验证电压施加到所选择的存储器单元，以对被编程为至少一个目标状态的存储器单元执行验证读取操作，其中第二验证电压被提供在指定的程序循环中并且随后 程序循环。 第二验证电压被设置为使得至少一个目标状态中的慢比特数目与另一目标状态下的慢比特数不同。
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公开(公告)号：US10482973B2
公开(公告)日：2019-11-19
申请号：US16014222
申请日：2018-06-21
发明人： Jae-Yun Lee , Joon Soo Kwon , Byung Soo Kim , Sang-Soo Park , Il Han Park , Jong-Hoon Lee
IPC分类号： G11C16/12 , H03K5/135 , G11C16/16 , G11C16/32 , G11C8/08 , G11C16/08 , H03K3/011 , G11C16/30 , G11C5/14 , G11C7/22 , G11C16/04
摘要： A memory device can include: a memory cell array including a memory cell and a word line that is connected to the memory cell; a clock generator configured to generate a first pumping clock signal from a system clock signal; a charge pump configured to provide a pumping voltage signal using a power supply voltage and the first pumping clock signal; a compensation circuit configured to compensate for variations in a first reference clock signal in accordance with variations in the power supply voltage, and provide a compensated first reference clock signal; and a pass/fail (P/F) determining circuit configured to determine whether the word line is defective by comparing the first pumping clock signal and the compensated first reference clock signal while the pumping voltage signal is provided to the word line.
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公开(公告)号：US10192620B2
公开(公告)日：2019-01-29
申请号：US15816903
申请日：2017-11-17
发明人： Wandong Kim , Sang-Soo Park , Se Hwan Park , Sang-Wan Nam
摘要： A nonvolatile memory device performs a method which includes: causing a ready/busy signal pin of the nonvolatile memory device to indicate that the nonvolatile memory device is in a precharge busy state wherein the nonvolatile memory device is not available to perform memory access operations for its nonvolatile memory cells; applying one or more word line precharge voltages to one or more selected word lines among a plurality of word lines of the nonvolatile memory device to precharge the selected word lines; and, after at least a portion of the precharge operation, causing the ready/busy signal pin to transition from indicating the precharge busy state, to indicating that the nonvolatile memory device is in a ready state wherein the nonvolatile memory device is available to perform memory access operations for its nonvolatile memory cells.
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公开(公告)号：US10134477B2
公开(公告)日：2018-11-20
申请号：US15625189
申请日：2017-06-16
发明人： Sang-Soo Park , Jaeyong Jeong
摘要： A nonvolatile memory device includes a memory cell array that stores data, and control logic. The control logic is configured to control a read operation, a program operation, or an erase operation on the data. The control logic is configured to detect a first power noise based on one of voltage sources to be provided to the memory cell array and a first reference voltage and detect a second power noise based on the one voltage source of the voltage sources and each of the first reference voltage and a second reference voltage. The control logic is configured to determine whether to perform at least one of an operation period of the read operation, an operation period of the program operation, or an operation period of the erase operation, based on whether at least one of the first and second power noises is detected.
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