公开(公告)号：US09299445B2

公开(公告)日：2016-03-29

申请号：US14746716

申请日：2015-06-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Il-Han Park ,  Go-Eun Jung

IPC: G11C7/10 ,  G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C7/10 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/3427

Abstract: A method of operating a nonvolatile memory device may include applying a first voltage greater than a ground voltage to a selected word line during a first time period; applying a second voltage to an unselected word line during a second time period that is later than the first time period; and applying a third voltage greater than the first voltage and the second voltage to the selected word line during the second time period. The second time period includes a third time period during which a voltage level of the unselected word line increases to the second voltage from a fourth voltage that is less than the second voltage, and during which a voltage level of the selected word line increases to the third voltage from the first voltage.

Abstract translation: 操作非易失性存储器件的方法可以包括在第一时间段期间将大于接地电压的第一电压施加到所选择的字线; 在比第一时间段晚的第二时间段期间将第二电压施加到未选择的字线; 以及在所述第二时间段期间将大于所述第一电压和所述第二电压的第三电压施加到所选择的字线。 第二时间段包括第三时间段，在该第三时间段期间，未选择字线的电压电平从小于第二电压的第四电压增加到第二电压，并且在此期间，所选字线的电压电平增加到 第一电压的第三电压。

公开(公告)号：US20200349986A1

公开(公告)日：2020-11-05

申请号：US16933768

申请日：2020-07-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Su Jang ,  Man-Jae Yang ,  Jeong-Don Ihm ,  Go-Eun Jung ,  Byung-Hoon Jeong ,  Young-Don Choi

IPC: G11C7/10 ,  G11C11/4096 ,  G11C7/22 ,  G11C11/4076

Abstract: A non-volatile memory device includes a serial pipeline structure connected to an output stage of a First In, First Out (FIFO) memory. The FIFO memory is configured to store data transmitted through a data path having a wave pipeline structure based on a plurality of FIFO input clock signals and output the stored data based on a plurality of FIFO output clock signals. A serializer is configured to output data to an input/output pad based on a select clock signal. The serial pipeline structure is connected between the FIFO memory and the serializer and configured to compensate for a phase difference between the data output from the FIFO memory and the select clock signal.

公开(公告)号：US09087590B2

公开(公告)日：2015-07-21

申请号：US13970462

申请日：2013-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Il-Han Park ,  Go-Eun Jung

IPC: G11C7/10 ,  G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C7/10 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/3427

Abstract: A nonvolatile memory device and a method of programming the nonvolatile semiconductor memory device are disclosed. The programming method includes applying a first voltage greater than a ground voltage to a selected word line at a first time; applying a second voltage greater than the first voltage to the selected word line at a second time that occurs after a predetermined period from the first time; applying the ground voltage to a first unselected word line directly adjacent to the selected word line at the first time; and applying a third voltage greater than the ground voltage to the first unselected word line at the second time.

Abstract translation: 公开了非易失性存储器件和非易失性半导体存储器件的编程方法。 编程方法包括：在第一时间向所选字线施加大于接地电压的第一电压; 在从第一次开始的预定时段之后的第二时间向所选择的字线施加大于第一电压的第二电压; 在第一次将接地电压施加到与所选字线直接相邻的第一未选字线; 以及在所述第二时间将大于所述接地电压的第三电压施加到所述第一未选择字线。

公开(公告)号：US10937471B2

公开(公告)日：2021-03-02

申请号：US16933768

申请日：2020-07-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Su Jang ,  Man-Jae Yang ,  Jeong-Don Ihm ,  Go-Eun Jung ,  Byung-Hoon Jeong ,  Young-Don Choi

IPC: G11C7/00 ,  G11C7/10 ,  G11C11/4096 ,  G11C7/22 ,  G11C11/4076 ,  G11C5/06 ,  G11C16/26

Abstract: A non-volatile memory device includes a serial pipeline structure connected to an output stage of a First In, First Out (FIFO) memory. The FIFO memory is configured to store data transmitted through a data path having a wave pipeline structure based on a plurality of FIFO input clock signals and output the stored data based on a plurality of FIFO output clock signals. A serializer is configured to output data to an input/output pad based on a select clock signal. The serial pipeline structure is connected between the FIFO memory and the serializer and configured to compensate for a phase difference between the data output from the FIFO memory and the select clock signal.

公开(公告)号：US10741225B2

公开(公告)日：2020-08-11

申请号：US16802084

申请日：2020-02-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Su Jang ,  Man-Jae Yang ,  Jeong-Don Ihm ,  Go-Eun Jung ,  Byung-Hoon Jeong ,  Young-Don Choi

IPC: G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  G11C16/26 ,  G11C5/06

Abstract: A non-volatile memory device includes a serial pipeline structure connected to an output stage of a First In, First Out (FIFO) memory. The FIFO memory is configured to store data transmitted through a data path having a wave pipeline structure based on a plurality of FIFO input clock signals and output the stored data based on a plurality of FIFO output clock signals. A serializer is configured to output data to an input/output pad based on a select clock signal. The serial pipeline structure is connected between the FIFO memory and the serializer and configured to compensate for a phase difference between the data output from the FIFO memory and the select clock signal.