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1.发明授权Non-volatile memory device having multi-level cells and method of forming the same 有权具有多电平电池的非易失性存储器件及其形成方法公开(公告)号：US09130160B2
公开(公告)日：2015-09-08
申请号：US14336007
申请日：2014-07-21
发明人： Gyu-Hwan Oh
CPC分类号： H01L45/1233 , G11C11/5678 , G11C13/0004 , G11C13/0069 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/126 , H01L45/1273 , H01L45/141 , H01L45/143 , H01L45/144 , H01L45/1683
摘要： A non-volatile memory device including multi-level cells is provided. The device includes first and second conductive patterns. Additionally, the device includes an electrode structure and a data storage pattern between the first and second conductive patterns. The data storage pattern may include a phase change material and a first vertical thickness of a first portion of the data storage pattern may be less than a second vertical thickness of a second portion of the data storage pattern. The electrode structure may include first and second electrodes and a vertical thickness of the first electrode may be greater than that of the second electrode.
摘要翻译： 提供了包括多级单元的非易失性存储器件。 该装置包括第一和第二导电图案。 另外，该装置包括在第一和第二导电图案之间的电极结构和数据存储图案。 数据存储图案可以包括相变材料，并且数据存储图案的第一部分的第一垂直厚度可以小于数据存储图案的第二部分的第二垂直厚度。 电极结构可以包括第一和第二电极，并且第一电极的垂直厚度可以大于第二电极的垂直厚度。
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公开(公告)号：US08790976B2
公开(公告)日：2014-07-29
申请号：US13942149
申请日：2013-07-15
发明人： Gyu-Hwan Oh , Sung-Lae Cho , Byoung-Jae Bae , Ik-Soo Kim , Dong-Hyun Im , Doo-Hwan Park , Kyoung-Ha Eom , Sung-Un Kwon , Chul-Ho Shin , Sang-Sup Jeong
IPC分类号： H01L21/336
CPC分类号： H01L45/1683 , H01L27/2463 , H01L45/06
摘要： A conductive pattern on a substrate is formed. An insulating layer having an opening exposing the conductive pattern is formed. A bottom electrode is formed on the conductive pattern and a first sidewall of the opening. A spacer is formed on the bottom electrode and a second sidewall of the opening. The spacer and the bottom electrode are formed to be lower than a top surface of the insulating layer. A data storage plug is formed on the bottom electrode and the spacer. The data storage plug has a first sidewall aligned with a sidewall of the bottom electrode and a second sidewall aligned with a sidewall of the spacer. A bit line is formed on the data storage plug.
摘要翻译： 形成基板上的导电图案。 形成具有露出导电图案的开口的绝缘层。 底部电极形成在导电图案和开口的第一侧壁上。 在底部电极和开口的第二侧壁上形成间隔物。 间隔件和底部电极形成为低于绝缘层的顶表面。 数据存储插头形成在底部电极和间隔件上。 数据存储插头具有与底部电极的侧壁对准的第一侧壁和与间隔件的侧壁对准的第二侧壁。 在数据存储插头上形成位线。
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公开(公告)号：US20200066799A1
公开(公告)日：2020-02-27
申请号：US16359146
申请日：2019-03-20
发明人： Dong-Jun Seong , Yong-Jin Park , Jun-Hwan Paik , Gyu-Hwan Oh
摘要： A variable resistance memory device may include a first conductive line, a plurality of stacked structures, and a mold pattern. The first conductive line may be formed on a substrate. The plurality of stacked structures may be formed on the first conductive line, and each of the plurality of stacked structures includes a lower electrode, a variable resistance pattern, and a middle electrode stacked on one another. The mold pattern may be formed on the first conductive line to fill a space between the plurality of stacked structures. An upper portion of the mold pattern may include a surface treated layer and a lower portion of the mold pattern may include a non-surface treated layer.
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公开(公告)号：US20130302966A1
公开(公告)日：2013-11-14
申请号：US13942149
申请日：2013-07-15
发明人： Gyu-Hwan Oh , Sung-Lae Cho , Byoung-Jae Bae , Ik-Soo Kim , Dong-Hyun Im , Doo-Hwan Park , Kyoung-Ha Eom , Sung-Un Kwon , Chul-Ho Shin , Sang-Sup Jeong
IPC分类号： H01L45/00
CPC分类号： H01L45/1683 , H01L27/2463 , H01L45/06
摘要： A conductive pattern on a substrate is formed. An insulating layer having an opening exposing the conductive pattern is formed. A bottom electrode is formed on the conductive pattern and a first sidewall of the opening. A spacer is formed on the bottom electrode and a second sidewall of the opening. The spacer and the bottom electrode are formed to be lower than a top surface of the insulating layer. A data storage plug is formed on the bottom electrode and the spacer. The data storage plug has a first sidewall aligned with a sidewall of the bottom electrode and a second sidewall aligned with a sidewall of the spacer. A bit line is formed on the data storage plug.
摘要翻译： 形成基板上的导电图案。 形成具有露出导电图案的开口的绝缘层。 底部电极形成在导电图案和开口的第一侧壁上。 在底部电极和开口的第二侧壁上形成间隔物。 间隔件和底部电极形成为低于绝缘层的顶表面。 数据存储插头形成在底部电极和间隔件上。 数据存储插头具有与底部电极的侧壁对准的第一侧壁和与间隔件的侧壁对准的第二侧壁。 在数据存储插头上形成位线。
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公开(公告)号：US20130256621A1
公开(公告)日：2013-10-03
申请号：US13735180
申请日：2013-01-07
发明人： Doo-Hwan Park , Gyu-Hwan Oh , Jeong-Min Park , Kyung-Min Chung
IPC分类号： H01L45/00
CPC分类号： H01L45/06 , H01L27/2409 , H01L27/2463 , H01L45/1233 , H01L45/126 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/1683
摘要： A phase-change memory device includes a diode, a plug, a doping layer pattern, a phase-change layer pattern and an upper electrode. The diode is disposed on a substrate. The plug is disposed on the diode and has a bottom surface whose area is equal to the area of a top surface of the diode. The plug is formed of metal or a conductive metallic compound. The doping layer pattern is disposed on the plug and has a bottom surface whose area is equal to the area of a top surface of the plug, and includes the same metal or conductive metallic compound as the plug. The phase-change layer pattern is disposed on the doping layer pattern. The upper electrode is disposed on the phase-change layer pattern.
摘要翻译： 相变存储器件包括二极管，插头，掺杂层图案，相变层图案和上电极。 二极管设置在基板上。 插头设置在二极管上，并具有面积等于二极管顶表面面积的底面。 插头由金属或导电金属化合物形成。 掺杂层图案设置在插塞上，并且具有面积等于插头顶面的面积的底面，并且包括与插头相同的金属或导电金属化合物。 相变层图案设置在掺杂层图案上。 上电极配置在相变层图案上。
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公开(公告)号：US10692933B2
公开(公告)日：2020-06-23
申请号：US16359146
申请日：2019-03-20
发明人： Dong-Jun Seong , Yong-Jin Park , Jun-Hwan Paik , Gyu-Hwan Oh
摘要： A variable resistance memory device may include a first conductive line, a plurality of stacked structures, and a mold pattern. The first conductive line may be formed on a substrate. The plurality of stacked structures may be formed on the first conductive line, and each of the plurality of stacked structures includes a lower electrode, a variable resistance pattern, and a middle electrode stacked on one another. The mold pattern may be formed on the first conductive line to fill a space between the plurality of stacked structures. An upper portion of the mold pattern may include a surface treated layer and a lower portion of the mold pattern may include a non-surface treated layer.
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