公开(公告)号：US20190139594A1

公开(公告)日：2019-05-09

申请号：US16032822

申请日：2018-07-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jang-Woo RYU ,  KYUNGRYUN KIM ,  SOO HWAN KIM ,  HUIKAP YANG

IPC: G11C11/4091 ,  G11C8/08 ,  G11C7/18 ,  G11C11/4097 ,  G11C11/4093 ,  G11C7/06

CPC classification number: G11C11/4091 ,  G11C5/025 ,  G11C7/06 ,  G11C7/065 ,  G11C7/1042 ,  G11C7/1048 ,  G11C7/18 ,  G11C8/08 ,  G11C11/4085 ,  G11C11/4093 ,  G11C11/4096 ,  G11C11/4097 ,  G11C2207/002

Abstract: A semiconductor memory device includes a cell array that includes a first row block and a second row block, a bit line sense amplifier block that senses data stored in the first row block or the second row block, a local sense amplifier that latches the sensed data transferred from the bit line sense amplifier block, and a switch that connects the local sense amplifier with a selected one of a first global data line and a second global data line in response to a select signal. The second row block may be placed at an edge of the cell array, and the switch connects the local sense amplifier with the first global data line when the first row block is activated and connects the local sense amplifier with the second global data line when the second row block is activated.