公开(公告)号：US20150036416A1

公开(公告)日：2015-02-05

申请号：US14315002

申请日：2014-06-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SOO HWAN KIM

IPC: G11C5/14 ,  G11C11/401

CPC classification number: G11C5/14 ,  G11C7/20

Abstract: A multi-channel memory device includes a first channel memory and a second channel memory that are independently accessible within a same chip and that respectively include first and second power channel connection lines; a decoupling unit that can operationally connect or separate the first and second power channel connection lines in response to a decoupling driving signal; and a switching control unit that can apply the decoupling driving signal to the decoupling unit in response to a channel power control signal such that power supply voltages independently applied to the first and second channel memories are respectively used in corresponding first and second power channel connection lines.

Abstract translation: 多通道存储器件包括第一通道存储器和第二通道存储器，其可在同一芯片内独立地访问，并且分别包括第一和第二电源通道连接线; 解耦单元，其可以响应于去耦驱动信号而可操作地连接或分离第一和第二电力通道连接线; 以及开关控制单元，其可以响应于信道功率控制信号将解耦驱动信号施加到去耦单元，使得独立地施加到第一和第二信道存储器的电源电压分别用于对应的第一和第二功率信道连接线路 。

公开(公告)号：US20190139594A1

公开(公告)日：2019-05-09

申请号：US16032822

申请日：2018-07-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jang-Woo RYU ,  KYUNGRYUN KIM ,  SOO HWAN KIM ,  HUIKAP YANG

IPC: G11C11/4091 ,  G11C8/08 ,  G11C7/18 ,  G11C11/4097 ,  G11C11/4093 ,  G11C7/06

CPC classification number: G11C11/4091 ,  G11C5/025 ,  G11C7/06 ,  G11C7/065 ,  G11C7/1042 ,  G11C7/1048 ,  G11C7/18 ,  G11C8/08 ,  G11C11/4085 ,  G11C11/4093 ,  G11C11/4096 ,  G11C11/4097 ,  G11C2207/002

Abstract: A semiconductor memory device includes a cell array that includes a first row block and a second row block, a bit line sense amplifier block that senses data stored in the first row block or the second row block, a local sense amplifier that latches the sensed data transferred from the bit line sense amplifier block, and a switch that connects the local sense amplifier with a selected one of a first global data line and a second global data line in response to a select signal. The second row block may be placed at an edge of the cell array, and the switch connects the local sense amplifier with the first global data line when the first row block is activated and connects the local sense amplifier with the second global data line when the second row block is activated.

公开(公告)号：US20170153831A1

公开(公告)日：2017-06-01

申请号：US15278078

申请日：2016-09-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： CHANKYUNG KIM ,  MIJO KIM ,  YONGGYU CHU ,  SEUNGBUM KO ,  SOO HWAN KIM

IPC: G06F3/06 ,  G06F11/07 ,  G11C29/52 ,  G11C11/16 ,  G11C11/4093

CPC classification number: G06F3/0619 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0673 ,  G06F3/0679 ,  G06F11/0727 ,  G06F11/0751 ,  G06F11/079 ,  G06F11/0793 ,  G11C5/147 ,  G11C7/1063 ,  G11C7/1066 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/16 ,  G11C7/20 ,  G11C7/222 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1693 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4093 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/4402

Abstract: A semiconductor memory device which stores operation environment information such as use time data, operating temperature data, or operating voltage data includes an internal circuit configured to perform a function set in the semiconductor memory device, and an operation environment information storing circuit configured to sense information about an operation environment of the semiconductor memory device when the semiconductor memory device operates, store the operation environment information in non-volatile memory cells, and provide the operation environment information stored in the non-volatile memory cells to an outside based on a request of reading out information.