公开(公告)号：US20170243973A1

公开(公告)日：2017-08-24

申请号：US15391888

申请日：2016-12-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungsam LEE ,  Junsoo KIM ,  Hyoshin AHN ,  Satoru YAMADA ,  Joohyun JEON ,  MoonYoung JEONG ,  Chunhyung CHUNG ,  Min Hee CHO ,  Kyo-Suk CHAE ,  Eunae CHOI

IPC: H01L29/78 ,  H01L29/04 ,  H01L29/423

CPC classification number: H01L29/7827 ,  H01L28/00 ,  H01L29/045 ,  H01L29/4236

Abstract: A semiconductor device including a semiconductor substrate including a trench, the semiconductor substrate having a crystal structure; and an insulating layer covering an inner sidewall of the trench, wherein the inner sidewall of the trench has at least one plane included in a {320} family of planes of the crystal structure or at least one plane similar to the {320} family of planes.

公开(公告)号：US20240379406A1

公开(公告)日：2024-11-14

申请号：US18394940

申请日：2023-12-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hee Sung LEE ,  Tae Sung KANG ,  Se Min YANG ,  Kyo-Suk CHAE ,  Seung Ho HONG ,  Beom Yong HWANG

IPC: H01L21/762 ,  H01L29/423 ,  H10B12/00

Abstract: A semiconductor device is disclosed. The semiconductor memory device comprises a substrate including an active region, an element isolation film disposed in the substrate and that defines the active region, a recess which is disposed in the active region and extends in a first direction, and a gate structure extending in a second direction, on the active region, wherein the gate structure includes a gate insulating film, a gate stack pattern, and a gate capping pattern which are sequentially stacked, wherein the gate insulating film extends along an upper face of the active region, and a part of the gate insulating film fills the recess, and wherein a height from a lower face of the substrate to a bottom face of the element isolation film is less than a height from the lower face of the substrate to a bottom face of the recess.

公开(公告)号：US20220085028A1

公开(公告)日：2022-03-17

申请号：US17332307

申请日：2021-05-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin A KIM ,  Ho-In RYU ,  Kyo-Suk CHAE ,  Joon Yong CHOE

IPC: H01L27/108

Abstract: A semiconductor device may include a substrate including trenches and contact recesses having a curved surface profile, conductive patterns in the trenches, buried contacts including first portions filling the contact recesses and second portions on the first portions, and spacer structures including first and second spacers. The second portions may have a pillar shape and a smaller width than top surfaces of the first portions. The buried contacts may be spaced apart from the conductive patterns by the spacer structures. The first spacers may be on the first portions of the buried contacts at outermost parts of the spacer structures. The first spacers may extend along the second portions of the buried contacts and contact the buried contacts. The second spacers may extend along the side surfaces of the conductive patterns and the trenches. The second spacers may contact the conductive patterns. The first spacers may include silicon oxide.

公开(公告)号：US20160322354A1

公开(公告)日：2016-11-03

申请号：US15209478

申请日：2016-07-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyo-Suk CHAE ,  Satoru YAMADA ,  Sang-Yeon HAN ,  Young-Jin CHOI ,  Wook-Je KIM

IPC: H01L27/088 ,  H01L23/535 ,  H01L27/02 ,  H01L29/423 ,  H01L29/08 ,  H01L29/06 ,  H01L29/49

CPC classification number: H01L27/088 ,  H01L23/535 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/7833

Abstract: A four transistor layout can include an isolation region that defines an active region, the active region extending along first and second different directions. A common source region of the four transistors extends from a center of the active region along both the first and second directions to define four quadrants of the active region that are outside the common source region. Four drain regions are provided, a respective one of which is in a respective one of the four quadrants and spaced apart from the common source region. Finally, four gate electrodes are provided, a respective one of which is in a respective one of the four quadrants between the common source region and a respective one of the four drain regions. A respective gate electrode includes a vertex and first and second extending portions, the first extending portions extending from the vertex along the first direction and the second extending portions extending from the vertex along the second direction.

Abstract translation: 四晶体管布局可以包括限定有源区域的隔离区域，有源区域沿第一和第二不同方向延伸。 四个晶体管的共同源极区域从有源区域的中心沿着第一和第二方向延伸，以限定位于公共源极区域外的有源区域的四个象限。 设置四个漏极区，其中的一个位于四个象限中的相应一个中并与公共源极区间隔开。 最后，提供四个栅电极，其中的一个位于公共源极区域和四个漏极区域中的相应一个之间的四个象限中的相应一个中。 相应的栅电极包括顶点和第一和第二延伸部分，第一延伸部分从顶点沿着第一方向延伸，第二延伸部分沿着第二方向从顶点延伸。