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    HOST FOR CONTROLLING NON-VOLATILE MEMORY CARD, SYSTEM INCLUDING THE SAME, AND METHODS OPERATING THE HOST AND THE SYSTEM
    1.
    发明申请
    HOST FOR CONTROLLING NON-VOLATILE MEMORY CARD, SYSTEM INCLUDING THE SAME, AND METHODS OPERATING THE HOST AND THE SYSTEM 审中-公开
    用于控制非易失性存储卡的主机，包括其的系统以及操作主机和系统的方法

    公开(公告)号：US20160306594A1

    公开(公告)日：2016-10-20

    申请号：US15191749

    申请日：2016-06-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyeong Min KIM ,  Hong Sik PARK ,  Hee Dong SHIN

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0611 ,  G06F3/0613 ,  G06F3/0656 ,  G06F3/0679 ,  G06F12/0246 ,  G06F13/1684 ,  G06F2221/2105 ,  G06F2221/2153

    Abstract: A host for controlling a non-volatile memory card, a system including the same, and methods of operating the host and the system are provided. The method of operating the host connected with the non-volatile memory card through a clock bus, a command bus, and one or more data buses includes transmitting a first command to the non-volatile memory card through the command bus, transmitting first data corresponding to the first command to the non-volatile memory card through the one or more data buses or receiving the first data from the non-volatile memory card through the data buses, and transmitting a second command to the non-volatile memory card at least once through the command bus during or before transfer of the first data.

    Abstract translation: 提供了用于控制非易失性存储卡的主机，包括其的系统以及操作主机和系统的方法。 通过时钟总线，命令总线和一个或多个数据总线来操作与非易失性存储卡连接的主机的方法包括：通过命令总线向第一命令发送第一命令到非易失性存储卡，发送对应的第一数据 通过所述一个或多个数据总线到所述非易失性存储卡的第一命令，或通过所述数据总线从所述非易失性存储卡接收所述第一数据，以及将至少一次的第二命令发送到所述非易失性存储卡 通过命令总线在传送第一个数据期间或之前。

    DATA TRANSMISSION APPARATUS FOR CHANGING CLOCK SIGNAL AT RUNTIME AND DATA INTERFACE SYSTEM INCLUDING THE SAME
    2.
    发明申请
    DATA TRANSMISSION APPARATUS FOR CHANGING CLOCK SIGNAL AT RUNTIME AND DATA INTERFACE SYSTEM INCLUDING THE SAME 审中-公开
    用于在运行期间更改时钟信号的数据传输装置和包括其的数据接口系统

    公开(公告)号：US20170041086A1

    公开(公告)日：2017-02-09

    申请号：US15223524

    申请日：2016-07-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seung Beom PARK ,  Hong Sik PARK ,  Jong Hyup LEE

    IPC: H04B15/02 ,  H04B17/00 ,  H03L7/07

    CPC classification number: H04B15/02 ,  H03L7/22 ,  H04B17/0085

    Abstract: In an example embodiment, a data transmission apparatus includes a transmission link module configured to generate a reference clock signal and a transmission D-PHY module. The transmission D-PHY module includes a first phase locked loop configured to receive the reference clock signal, and generate a first clock signal. The transmission D-PHY module further includes a second phase locked loop configured to receive the reference clock signal, and generate a second clock signal having a different frequency than the first clock signal. The transmission D-PHY module further includes a multiplexer configured to select and output one of the first and second clock signals as a clock signal according to a selection signal. The transmission D-PHY module further includes a data transmitter configured to convert parallel data into serial data in response to the clock signal for transmission to a receiver.

    Abstract translation: 在示例实施例中，数据传输装置包括被配置为产生参考时钟信号和传输D-PHY模块的传输链路模块。 传输D-PHY模块包括被配置为接收参考时钟信号并产生第一时钟信号的第一锁相环。 传输D-PHY模块还包括被配置为接收参考时钟信号并产生具有与第一时钟信号不同的频率的第二时钟信号的第二锁相环。 传输D-PHY模块还包括多路复用器，其被配置为根据选择信号选择并输出第一和第二时钟信号中的一个作为时钟信号。 传输D-PHY模块还包括数据发射机，其被配置为响应于时钟信号将并行数据转换为串行数据，以传输到接收机。

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