公开(公告)号：US20240363634A1

公开(公告)日：2024-10-31

申请号：US18732767

申请日：2024-06-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Inchan HWANG ,  Seunghyun SONG ,  Byounghak HONG

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/8238 ,  H01L23/535 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L27/0922 ,  H01L21/0259 ,  H01L21/823807 ,  H01L21/823871 ,  H01L23/535 ,  H01L27/0924 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78696

Abstract: A multi-stack semiconductor device includes: a lower-stack transistor structure including a lower active region and a lower gate structure, the lower active region including a lower channel structure, and the lower gate structure surrounding the lower channel structure; an upper-stack transistor structure vertically stacked above the lower-stack transistor structure, and including an upper active region and an upper gate structure, the upper active region including an upper channel structure, and the upper gate structure surrounding the upper channel structure; and at least one gate contact plug contacting a top surface of the lower gate structure, wherein the lower gate structure and the upper gate structure have a substantially same size in a plan view, and wherein the lower gate structure is not entirely overlapped by the upper gate structure in a vertical direction.

公开(公告)号：US20240357787A1

公开(公告)日：2024-10-24

申请号：US18540008

申请日：2023-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Inchan HWANG ,  Kyung Hee CHO ,  Seunghun LEE

IPC: H10B10/00 ,  H01L23/522 ,  H01L23/528 ,  H01L29/423

CPC classification number: H10B10/12 ,  H01L23/5226 ,  H01L23/5286 ,  H01L29/4232

Abstract: A semiconductor memory device comprising a substrate having first and second surfaces opposite to each other, a lower active region on the first surface and including a first lower gate electrode and a first lower active contact, an upper active region on the lower active region and including a first upper gate electrode and a first upper active contact that vertically overlap at least a part of the first lower active contact, a first connection structure vertically connecting the first upper active contact to the first lower active contact, a first metal layer on the first surface, and a backside metal layer on the second surface. The first upper gate electrode and the first lower gate electrode are connected and form a first gate electrode. The first metal layer includes a first node line electrically connecting the first gate electrode to the first upper active contact.

公开(公告)号：US20220109046A1

公开(公告)日：2022-04-07

申请号：US17146136

申请日：2021-01-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounghak HONG ,  Seunghyun SONG ,  Kang III SEO ,  Hwichan JUN ,  Inchan HWANG

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/423 ,  H01L29/786 ,  H01L29/417

Abstract: A semiconductor device include: a substrate; a 1st transistor formed above the substrate, the 1st transistor including a 1st channel set of a plurality of 1st nanosheet layers, a 1st gate structure surrounding the 1st nanosheet layers, and 1st and 2nd source/drain regions at both ends of the 1st channel set; and a 2nd transistor formed above the 1st transistor in a vertical direction, the 2nd transistor including a 2nd channel set of a plurality of 2nd nanosheet layers, a 2nd gate structure surrounding the 2nd nanosheet layers, and 3rd and 4th source/drain regions at both ends of the 2nd channel set, wherein the 1st channel set has a greater width than the 2nd channel set, wherein a number of the 1st nanosheet layers is smaller than a number of the 2nd nanosheet layers, and wherein a sum of effective channel widths of the 1st nanosheet layers is substantially equal to a sum of effective channel width of the 2nd nanosheet layers.

公开(公告)号：US20250031360A1

公开(公告)日：2025-01-23

申请号：US18905663

申请日：2024-10-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounghak HONG ,  Seunghyun SONG ,  Saehan PARK ,  Seungyoung LEE ,  Inchan HWANG

IPC: H10B10/00 ,  H01L21/762 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A multi-stack semiconductor device includes: a plurality of lower transistor structures arranged on a lower stack and including a plurality of lower fin structures surrounded by a plurality of lower gate structures, respectively; a plurality of upper transistor structures arranged on an upper stack and including a plurality of upper fin structures surrounded by a plurality of upper gate structures, respectively; and at least one of a lower diffusion break structure on the lower stack and a upper diffusion break structure on the upper stack, wherein the lower diffusion break structure is formed between two adjacent lower gate structures, and isolates two lower transistor structures respectively including the two adjacent lower gate structures from each other, and the upper diffusion break structure is formed between two adjacent upper gate structures, and isolates two upper transistor structures respectively including the two adjacent upper gate structures from each other.

公开(公告)号：US20240258437A1

公开(公告)日：2024-08-01

申请号：US18510146

申请日：2023-11-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jisoo PARK ,  Donghoon HWANG ,  Inchan HWANG ,  Hyojin KIM ,  Jaehyoung LIM

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L29/78696 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775

Abstract: A 3D stacked FET may include a back-side wiring layer including a first back-side power line and a second back-side power line, a first FET on the back-side wiring layer, a second FET over the first FET, a front-side wiring layer over the second FET, a first through-electrode connecting the first FET to the second FET, and a second through-electrode connecting the front-side and back-side power lines. The front-side wiring layer may extend in a first direction and may include a front-side power line connected to the second back-side power line. The first FET and the second FET may share a gate extending in a second direction. Each of the first FET and the second FET may include a source and a drain respectively on both sides of the gate in the first direction, and a channel between the source and the drain and surrounded by the gate.

公开(公告)号：US20190157406A1

公开(公告)日：2019-05-23

申请号：US16014496

申请日：2018-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Inchan HWANG ,  Heonjong SHIN ,  Sunghun JUNG ,  Doohyun LEE ,  Hwichan JUN ,  Hakyoon AHN

IPC: H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L27/092 ,  H01L21/285 ,  H01L29/06 ,  H01L29/66

Abstract: A semiconductor device is disclosed. The semiconductor device may include a substrate including a first active pattern, the first active pattern vertically protruding from a top surface of the substrate, a first source/drain pattern filling a first recess, which is formed in an upper portion of the first active pattern, a first metal silicide layer on the first source/drain pattern, the first metal silicide layer including a first portion and a second portion, which are located on a first surface of the first source/drain pattern, and a first contact in contact with the second portion of the first metal silicide layer. A thickness of the first portion may be different from a thickness of the second portion.

公开(公告)号：US20220359500A1

公开(公告)日：2022-11-10

申请号：US17866066

申请日：2022-07-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Inchan HWANG ,  Hwichan JUN

IPC: H01L27/085 ,  H01L21/8234 ,  H01L21/822

Abstract: An array of multi-stack transistor structures is provided, wherein the multi-stack transistor structures are arranged in a plurality of rows and a plurality of columns in the array, wherein each of the multi-stack transistor structures includes two or more vertically arranged transistor stacks, and wherein a dam structure is formed between adjacent two rows in a same column so that a multi-stack transistor structure in one of the adjacent two rows is electrically isolated from a multi-stack transistor structure in the other of the adjacent two rows in the same column.

公开(公告)号：US20220246623A1

公开(公告)日：2022-08-04

申请号：US17239060

申请日：2021-04-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Inchan HWANG ,  Hwichan JUN

IPC: H01L27/11 ,  H01L23/528 ,  H01L27/092 ,  H01L21/8238

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a static random access memory (SRAM) including a plurality of transistors disposed in a first layer and a second layer. The first layer includes a first shared gate of a first transistor and a second shared gate of a second transistor, among the plurality of transistors. The second layer is disposed above the first layer and includes a third shared gate of a third transistor and a fourth shared gate of a fourth transistor, among the plurality of transistors. The third shared gate is disposed above the first shared gate, and the fourth shared gate is disposed above the second shared gate. The SRAM further includes a first shared contact, a second shared contact, a first cross-couple contact connecting the fourth shared gate and the first shared contact, and a second cross-couple contact connecting the third shared gate and the second shared contact.

公开(公告)号：US20220108981A1

公开(公告)日：2022-04-07

申请号：US17147587

申请日：2021-01-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Inchan HWANG ,  Hwichan JUN

IPC: H01L27/085 ,  H01L21/822 ,  H01L21/8234

Abstract: An array of multi-stack transistor structures is provided, wherein the multi-stack transistor structures are arranged in a plurality of rows and a plurality of columns in the array, wherein each of the multi-stack transistor structures includes two or more vertically arranged transistor stacks, and wherein a dam structure is formed between adjacent two rows in a same column so that a multi-stack transistor structure in one of the adjacent two rows is electrically isolated from a multi-stack transistor structure in the other of the adjacent two rows in the same column.

公开(公告)号：US20240274686A1

公开(公告)日：2024-08-15

申请号：US18437473

申请日：2024-02-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byungho MOON ,  Inchan HWANG ,  Doyoung CHOI

IPC: H01L29/423 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L21/823437 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

Abstract: A stacked integrated circuit device, including a lower active region, a lower gate pattern surrounding the lower active region, a lower dielectric layer between the lower active region and the lower gate pattern, an intermediate insulating layer on the lower active region, an upper active region on the intermediate insulating layer, an upper gate pattern surrounding the upper active region and covering the lower gate pattern, and an upper dielectric layer between the upper active region and the upper gate pattern, wherein an upper surface of the lower gate pattern is located lower in a vertical direction than an upper surface of the intermediate insulating layer, and the lower gate pattern surrounds at least a portion of a side surface of the intermediate insulating layer.