公开(公告)号：US20160086841A1

公开(公告)日：2016-03-24

申请号：US14711394

申请日：2015-05-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEUNGHYUN SONG ,  Hyeon Kyun Noh ,  Taeyong Kwon ,  Sangsu Kim ,  Shigenobu Maeda ,  Krishna Bhuwalka ,  Uihui Kwon ,  Keunho Lee ,  Wonsok Lee

IPC: H01L21/762 ,  H01L29/10 ,  H01L21/02 ,  H01L29/06 ,  H01L21/308 ,  H01L29/66

CPC classification number: H01L21/76224 ,  H01L21/3086 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method for forming a pattern of a semiconductor device and a semiconductor device formed using the same are provided. The method includes forming a buffer layer on a substrate, forming a channel layer on the buffer layer, forming support patterns penetrating the channel layer, and forming channel fin patterns and a buffer pattern by patterning the channel layer and the buffer layer. The channel layer includes a material of which a lattice constant is different from that of the buffer layer, and each of the channel fin patterns has both sidewalls that are in contact with the support patterns and are opposite to each other.

Abstract translation: 提供了一种用于形成半导体器件的图案的方法和使用其形成的半导体器件。 该方法包括在衬底上形成缓冲层，在缓冲层上形成沟道层，形成穿透沟道层的支撑图案，并通过图案化沟道层和缓冲层形成沟道鳍图案和缓冲图案。 沟道层包括晶格常数与缓冲层的晶格常数不同的材料，并且每个沟道鳍图案具有与支撑图案接触并且彼此相对的两个侧壁。

公开(公告)号：US11574095B2

公开(公告)日：2023-02-07

申请号：US16906038

申请日：2020-06-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanghoon Myung ,  Hyunjae Jang ,  In Huh ,  Hyeon Kyun Noh ,  Min-Chul Park ,  Changwook Jeong

IPC: G06F30/27 ,  G06N3/08 ,  G06N3/10 ,  G06N3/04 ,  G06F30/398

Abstract: Provided is a simulation method performed by a process simulator, implemented with a recurrent neural network (RNN) including a plurality of process emulation cells, which are arranged in time series and configured to train and predict, based on a final target profile, a profile of each process step included in a semiconductor manufacturing process. The simulation method includes: receiving, at a first process emulation cell, a previous output profile provided at a previous process step, a target profile and process condition information of a current process step; and generating, at the first process emulation cell, a current output profile corresponding to the current process step, based on the target profile, the process condition information, and prior knowledge information, the prior knowledge information defining a time series causal relationship between the previous process step and the current process step.

公开(公告)号：US11886783B2

公开(公告)日：2024-01-30

申请号：US18153573

申请日：2023-01-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanghoon Myung ,  Hyunjae Jang ,  In Huh ,  Hyeon Kyun Noh ,  Min-Chul Park ,  Changwook Jeong

IPC: G06F30/27 ,  G06N3/08 ,  G06N3/10 ,  G06F30/398 ,  G06N3/044

CPC classification number: G06F30/27 ,  G06F30/398 ,  G06N3/044 ,  G06N3/08 ,  G06N3/10

Abstract: Provided is a simulation method performed by a process simulator, implemented with a recurrent neural network (RNN) including a plurality of process emulation cells, which are arranged in time series and configured to train and predict, based on a final target profile, a profile of each process step included in a semiconductor manufacturing process. The simulation method includes: receiving, at a first process emulation cell, a previous output profile provided at a previous process step, a target profile and process condition information of a current process step; and generating, at the first process emulation cell, a current output profile corresponding to the current process step, based on the target profile, the process condition information, and prior knowledge information, the prior knowledge information defining a time series causal relationship between the previous process step and the current process step.

公开(公告)号：US20230142367A1

公开(公告)日：2023-05-11

申请号：US18153573

申请日：2023-01-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanghoon MYUNG ,  Hyunjae Jang ,  In Huh ,  Hyeon Kyun Noh ,  Min-Chul Park ,  Changwook Jeong

IPC: G06F30/27 ,  G06N3/08 ,  G06N3/10 ,  G06F30/398 ,  G06N3/044

CPC classification number: G06F30/27 ,  G06N3/08 ,  G06N3/10 ,  G06F30/398 ,  G06N3/044

Abstract: Provided is a simulation method performed by a process simulator, implemented with a recurrent neural network (RNN) including a plurality of process emulation cells, which are arranged in time series and configured to train and predict, based on a final target profile, a profile of each process step included in a semiconductor manufacturing process. The simulation method includes: receiving, at a first process emulation cell, a previous output profile provided at a previous process step, a target profile and process condition information of a current process step; and generating, at the first process emulation cell, a current output profile corresponding to the current process step, based on the target profile, the process condition information, and prior knowledge information, the prior knowledge information defining a time series causal relationship between the previous process step and the current process step.

公开(公告)号：US11282833B2

公开(公告)日：2022-03-22

申请号：US16660976

申请日：2019-10-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong Jin Lee ,  Ji Young Kim ,  Bong Soo Kim ,  Hyeon Kyun Noh ,  Moon Young Jeong

IPC: H01L27/06 ,  H01L27/108 ,  H01L27/12 ,  H01L29/22

Abstract: A semiconductor device is provided. The semiconductor device includes a first substrate, an active region defined by an isolation film in the first substrate, an oxide semiconductor layer on the first substrate in the active region, and not comprising silicon, a recess inside the oxide semiconductor layer, and a gate structure filling the recess, comprising a gate electrode and a capping film on the gate electrode, and having an upper surface on a same plane as an upper surface of the active region.

公开(公告)号：US20210158152A1

公开(公告)日：2021-05-27

申请号：US16906038

申请日：2020-06-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanghoon MYUNG ,  Hyunjae Jang ,  In Huh ,  Hyeon Kyun Noh ,  Min-chul Park ,  Changwook Jeong

IPC: G06N3/08 ,  G06N3/04 ,  G06N3/10

Abstract: Provided is a simulation method performed by a process simulator, implemented with a recurrent neural network (RNN) including a plurality of process emulation cells, which are arranged in time series and configured to train and predict, based on a final target profile, a profile of each process step included in a semiconductor manufacturing process. The simulation method includes: receiving, at a first process emulation cell, a previous output profile provided at a previous process step, a target profile and process condition information of a current process step; and generating, at the first process emulation cell, a current output profile corresponding to the current process step, based on the target profile, the process condition information, and prior knowledge information, the prior knowledge information defining a time series causal relationship between the previous process step and the current process step.