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    Semiconductor memory devices, memory systems and methods of operating semiconductor memory devices
    1.
    发明授权
    Semiconductor memory devices, memory systems and methods of operating semiconductor memory devices 有权

    公开(公告)号：US11557332B2

    公开(公告)日：2023-01-17

    申请号：US17322227

    申请日：2021-05-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sang-Uhn Cha ,  Hyun-Gi Kim ,  Hoon Sin ,  Ye-Sin Ryu ,  In-Woo Jun

    IPC: G11C7/00 ,  G11C11/406 ,  G06F11/10

    Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a refresh control circuit, a scrubbing control circuit and a control logic circuit. The refresh control circuit generates refresh row addresses for refreshing a memory region on memory cell rows in response to a first command received from a memory controller. The scrubbing control circuit counts the refresh row addresses and generates a scrubbing address for performing a scrubbing operation on a first memory cell row of the memory cell rows whenever the scrubbing control circuit counts N refresh row addresses of the refresh row addresses. The ECC engine reads first data corresponding to a first codeword, from at least one sub-page in the first memory cell row, corrects at least one error bit in the first codeword and writes back the corrected first codeword in a corresponding memory location.

    Semiconductor memory devices, memory systems and methods of operating semiconductor memory devices
    3.
    发明授权
    Semiconductor memory devices, memory systems and methods of operating semiconductor memory devices 有权

    公开(公告)号：US10811078B2

    公开(公告)日：2020-10-20

    申请号：US16779194

    申请日：2020-01-31

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sang-Uhn Cha ,  Hyun-Gi Kim ,  Hoon Sin ,  Ye-Sin Ryu ,  In-Woo Jun

    IPC: G01C7/00 ,  G11C11/406 ,  G06F11/10

    Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a refresh control circuit, a scrubbing control circuit and a control logic circuit. The refresh control circuit generates refresh row addresses for refreshing a memory region on memory cell rows in response to a first command received from a memory controller. The scrubbing control circuit counts the refresh row addresses and generates a scrubbing address for performing a scrubbing operation on a first memory cell row of the memory cell rows whenever the scrubbing control circuit counts N refresh row addresses of the refresh row addresses. The ECC engine reads first data corresponding to a first codeword, from at least one sub-page in the first memory cell row, corrects at least one error bit in the first codeword and writes back the corrected first codeword in a corresponding memory location.

    Semiconductor semiconductor memory devices, memory systems and methods of operating memory devices
    8.
    发明授权
    Semiconductor semiconductor memory devices, memory systems and methods of operating memory devices 有权

    公开(公告)号：US10586584B2

    公开(公告)日：2020-03-10

    申请号：US16228518

    申请日：2018-12-20

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sang-Uhn Cha ,  Hyun-Gi Kim ,  Hoon Sin ,  Ye-Sin Ryu ,  In-Woo Jun

    IPC: G11C7/00 ,  G11C11/406 ,  G06F11/10

    Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a refresh control circuit, a scrubbing control circuit and a control logic circuit. The refresh control circuit generates refresh row addresses for refreshing a memory region on memory cell rows in response to a first command received from a memory controller. The scrubbing control circuit counts the refresh row addresses and generates a scrubbing address for performing a scrubbing operation on a first memory cell row of the memory cell rows whenever the scrubbing control circuit counts N refresh row addresses of the refresh row addresses. The ECC engine reads first data corresponding to a first codeword, from at least one sub-page in the first memory cell row, corrects at least one error bit in the first codeword and writes back the corrected first codeword in a corresponding memory location.

    Semiconductor memory devices with error correction and methods of operating the same
    9.
    发明授权
    Semiconductor memory devices with error correction and methods of operating the same 有权

    公开(公告)号：US10387276B2

    公开(公告)日：2019-08-20

    申请号：US15596540

    申请日：2017-05-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ye-Sin Ryu ,  Jong-Wook Park ,  Youn-Hyung Kang

    IPC: G11C29/00 ,  G06F11/16 ,  G06F3/06 ,  G06F11/10 ,  G11C29/52 ,  G11C29/04

    Abstract: A method of operating a semiconductor memory device including a memory cell array and an error correction code (ECC) engine, wherein the memory cell array includes a plurality of memory cells and the ECC engine is configured to perform an error correction operation on data of the memory cell array, may include storing, in a nonvolatile storage, a mapping information indicating physical addresses of normal cells to swap with a portion of fail cells when a first unit of memory cells includes a number of the fail cells exceeding an error correction capability of the ECC engine. The first unit of memory cells of the memory cells may be accessed based on a logical address. The method may include performing a memory operation on the memory cell array selectively based on the mapping information.

    Semiconductor memory devices and methods of operating the same
    10.
    发明授权
    Semiconductor memory devices and methods of operating the same 有权

    公开(公告)号：US10156995B2

    公开(公告)日：2018-12-18

    申请号：US15398409

    申请日：2017-01-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sang-Uhn Cha ,  Hoi-Ju Chung ,  Ye-Sin Ryu ,  Seong-Jin Cho

    IPC: G06F3/06 ,  H03M13/15 ,  G11C29/52 ,  G11C11/16 ,  G06F11/10 ,  H03M13/00 ,  G11C29/00 ,  G11C29/04

    Abstract: A semiconductor memory device includes a memory cell array, a control logic circuit, and an error correction circuit. The control logic circuit generates control signals by decoding a command. The control logic circuit, in a write mode of the semiconductor memory device, controls the error correction circuit to read a first unit of data from a selected sub-page and to generate a first parity data based on one of the first sub unit of data and the second sub unit of data and a main data to be written into the sub-page while generating syndrome data by performing an error correction code decoding on the first unit of data. The error correction circuit, when a first sub unit of data includes at least one error bit, selectively modifies the first parity data based on a data mask signal associated with the main data.

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