公开(公告)号：US09165820B2

公开(公告)日：2015-10-20

申请号：US14451650

申请日：2014-08-05

Applicant: Samsung Electronics Co., Ltd

Inventor： Jeeyong Kim ,  Hyunchul Back ,  Jung-Hwan Lee ,  Hyunmin Lee

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/522

CPC classification number: H01L21/7682 ,  H01L21/76877 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5222 ,  H01L27/11524 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices and methods of fabricating the same are provided. The semiconductor device may include interconnections extending in a first direction on a substrate and spaced apart from each other in a second direction perpendicular to the first direction, barrier dielectric patterns disposed on top surfaces of the interconnections, respectively, and an upper interlayer dielectric layer disposed on the interconnection. Respective air gaps are disposed between adjacent ones of the interconnections.

Abstract translation: 提供半导体器件及其制造方法。 半导体器件可以包括在衬底上沿着第一方向延伸并且在垂直于第一方向的第二方向彼此间隔开的互连，分别设置在互连的顶表面上的势垒电介质图案和布置在 在互连上。 相应的气隙设置在相邻的互连之间。

公开(公告)号：US20130228934A1

公开(公告)日：2013-09-05

申请号：US13779174

申请日：2013-02-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeeyong KIM ,  Hyunchul Back ,  Jung-Hwan Lee ,  Hyunmin Lee

IPC: H01L23/48

CPC classification number: H01L21/7682 ,  H01L21/76877 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5222 ,  H01L27/11524 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices and methods of fabricating the same are provided. The semiconductor device may include interconnections extending in a first direction on a substrate and spaced apart from each other in a second direction perpendicular to the first direction, barrier dielectric patterns disposed on top surfaces of the interconnections, respectively, and an upper interlayer dielectric layer disposed on the interconnection. Respective air gaps are disposed between adjacent ones of the interconnections.

Abstract translation: 提供半导体器件及其制造方法。 半导体器件可以包括在衬底上沿着第一方向延伸并且在垂直于第一方向的第二方向彼此间隔开的互连，分别设置在互连的顶表面上的势垒电介质图案和布置在 在互连上。 相应的气隙设置在相邻的互连之间。

公开(公告)号：US10186519B2

公开(公告)日：2019-01-22

申请号：US15059993

申请日：2016-03-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongwon Kim ,  Hyeong Park ,  Hyunmin Lee ,  Hojong Kang ,  Joowon Park ,  Seungmin Song

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11575

Abstract: A semiconductor memory device includes a stack structure including gate electrodes vertically stacked on a substrate and a vertical channel part penetrating the gate electrodes, a bit line connected to the vertical channel part, and a plurality of conductive lines connected to the gate electrodes on the stack structure. The conductive lines form a plurality of stacked layers and include first conductive lines and second conductive lines. The number of the first conductive lines disposed at a first level from the substrate is different from the number of the second conductive lines disposed at a second level from the substrate. The first level is different from the second level.

公开(公告)号：US08829682B2

公开(公告)日：2014-09-09

申请号：US13779174

申请日：2013-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeeyong Kim ,  Hyunchul Back ,  Jung-Hwan Lee ,  Hyunmin Lee

IPC: H01L23/48

CPC classification number: H01L21/7682 ,  H01L21/76877 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5222 ,  H01L27/11524 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices and methods of fabricating the same are provided. The semiconductor device may include interconnections extending in a first direction on a substrate and spaced apart from each other in a second direction perpendicular to the first direction, barrier dielectric patterns disposed on top surfaces of the interconnections, respectively, and an upper interlayer dielectric layer disposed on the interconnection. Respective air gaps are disposed between adjacent ones of the interconnections.

Abstract translation: 提供半导体器件及其制造方法。 半导体器件可以包括在衬底上沿着第一方向延伸并且在垂直于第一方向的第二方向彼此间隔开的互连，分别设置在互连的顶表面上的势垒电介质图案和布置在 在互连上。 相应的气隙设置在相邻的互连之间。

公开(公告)号：US10685977B2

公开(公告)日：2020-06-16

申请号：US16231710

申请日：2018-12-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongwon Kim ,  Hyeong Park ,  Hyunmin Lee ,  Hojong Kang ,  Joowon Park ,  Seungmin Song

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11575

Abstract: A semiconductor memory device includes a stack structure including gate electrodes vertically stacked on a substrate and a vertical channel part penetrating the gate electrodes, a bit line connected to the vertical channel part, and a plurality of conductive lines connected to the gate electrodes on the stack structure. The conductive lines form a plurality of stacked layers and include first conductive lines and second conductive lines. The number of the first conductive lines disposed at a first level from the substrate is different from the number of the second conductive lines disposed at a second level from the substrate. The first level is different from the second level.

公开(公告)号：USD875742S1

公开(公告)日：2020-02-18

申请号：US29645605

申请日：2018-04-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Designer： Minji Kang ,  Jingyu Seo ,  Jihye Kim ,  Hyunmin Lee

公开(公告)号：US20140342548A1

公开(公告)日：2014-11-20

申请号：US14451650

申请日：2014-08-05

Applicant: Samsung Electronics Co., Ltd

Inventor： Jeeyong Kim ,  Hyunchul Back ,  Jung-Hwan Lee ,  Hyunmin Lee

IPC: H01L21/768

CPC classification number: H01L21/7682 ,  H01L21/76877 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5222 ,  H01L27/11524 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices and methods of fabricating the same are provided. The semiconductor device may include interconnections extending in a first direction on a substrate and spaced apart from each other in a second direction perpendicular to the first direction, barrier dielectric patterns disposed on top surfaces of the interconnections, respectively, and an upper interlayer dielectric layer disposed on the interconnection. Respective air gaps are disposed between adjacent ones of the interconnections.

Abstract translation: 提供半导体器件及其制造方法。 半导体器件可以包括在衬底上沿着第一方向延伸并且在垂直于第一方向的第二方向彼此间隔开的互连，分别设置在互连的顶表面上的势垒电介质图案和布置在 在互连上。 相应的气隙设置在相邻的互连之间。