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公开(公告)号：US12125791B2
公开(公告)日：2024-10-22
申请号：US17209657
申请日：2021-03-23
发明人： Jeeyong Kim , Junghwan Lee
IPC分类号： H01L23/535 , H01L21/768 , H01L23/522 , H01L23/528 , H10B41/27 , H10B41/41 , H10B43/27 , H10B43/40
CPC分类号： H01L23/535 , H01L21/76805 , H01L21/76889 , H01L21/76895 , H01L23/5226 , H01L23/5283 , H10B41/27 , H10B41/41 , H10B43/27 , H10B43/40
摘要： A semiconductor device includes: a substrate including a memory cell region and a connection region; a plurality of gate lines vertically overlapping each other in the memory cell region of the substrate in a vertical direction, each gate line including a first metal; a stepped connection unit in the connection region and comprising a plurality of conductive pad regions, each conductive pad region including the first metal and integrally connected to a respective gate line of the plurality of gate lines; a plurality of contact structures vertically overlapping the stepped connection unit, each contact structure connected to a respectively corresponding conductive pad region of the plurality of conductive pad regions and including a second metal; and at least one metal silicide layer between at least one contact structure and the respectively corresponding conductive pad region.
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2.发明授权公开(公告)号：US08829682B2
公开(公告)日：2014-09-09
申请号：US13779174
申请日：2013-02-27
发明人： Jeeyong Kim , Hyunchul Back , Jung-Hwan Lee , Hyunmin Lee
IPC分类号： H01L23/48
CPC分类号： H01L21/7682 , H01L21/76877 , H01L23/481 , H01L23/522 , H01L23/5222 , H01L27/11524 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices and methods of fabricating the same are provided. The semiconductor device may include interconnections extending in a first direction on a substrate and spaced apart from each other in a second direction perpendicular to the first direction, barrier dielectric patterns disposed on top surfaces of the interconnections, respectively, and an upper interlayer dielectric layer disposed on the interconnection. Respective air gaps are disposed between adjacent ones of the interconnections.
摘要翻译： 提供半导体器件及其制造方法。 半导体器件可以包括在衬底上沿着第一方向延伸并且在垂直于第一方向的第二方向彼此间隔开的互连，分别设置在互连的顶表面上的势垒电介质图案和布置在 在互连上。 相应的气隙设置在相邻的互连之间。
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公开(公告)号：US20130260554A1
公开(公告)日：2013-10-03
申请号：US13905375
申请日：2013-05-30
发明人： Jeeyong Kim , Woonkyung Lee , Sunggil Kim , Jin-Kyu Kang , Jung-Hwan Lee , Bonyoung Koo , Kihyun Hwang , Byoungsun Ju , Jintae Noh
IPC分类号： H01L21/768 , H01L21/28
CPC分类号： H01L27/11526 , H01L21/28 , H01L21/76841 , H01L23/48 , H01L23/535 , H01L27/11521 , H01L27/11568 , H01L27/11573 , H01L29/4958 , H01L29/78 , H01L29/788 , H01L29/7883 , H01L29/792 , H01L2924/0002 , H01L2924/00
摘要： Provided are a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a charge storage pattern formed on a substrate; a dielectric pattern formed on the charge storage pattern; a first conductive pattern including silicon doped with a first impurity of a first concentration, the first conductive pattern being disposed on the dielectric pattern; and a second conductive pattern including metal silicide doped with a second impurity of a second concentration, the second conductive pattern being disposed on the first conductive pattern. The first concentration may be higher than the second concentration.
摘要翻译： 提供半导体器件和制造半导体器件的方法。 半导体器件包括形成在衬底上的电荷存储图案; 形成在电荷存储图案上的电介质图案; 第一导电图案，包括掺杂有第一浓度的第一杂质的硅，所述第一导电图案设置在所述电介质图案上; 以及第二导电图案，其包括掺杂有第二浓度的第二杂质的金属硅化物，所述第二导电图案设置在所述第一导电图案上。 第一浓度可能高于第二浓度。
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公开(公告)号：US11903199B2
公开(公告)日：2024-02-13
申请号：US17351486
申请日：2021-06-18
发明人： Jeeyong Kim , Junghwan Lee
摘要： A through via structure includes a through via and a capping pattern. The through via includes a metal pattern extending in a vertical direction, and a barrier pattern on a sidewall and a lower surface of the metal pattern. The capping pattern contacts an upper surface of the through via. A lowermost surface of an edge portion of the capping pattern is not higher than a lowermost surface of a central portion of the capping pattern.
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5.发明申请Integrated Circuit Devices Including Interconnections Insulated by Air Gaps and Methods of Fabricating the Same 审中-公开包括由空气间隙绝缘的互连的集成电路器件及其制造方法公开(公告)号：US20140342548A1
公开(公告)日：2014-11-20
申请号：US14451650
申请日：2014-08-05
发明人： Jeeyong Kim , Hyunchul Back , Jung-Hwan Lee , Hyunmin Lee
IPC分类号： H01L21/768
CPC分类号： H01L21/7682 , H01L21/76877 , H01L23/481 , H01L23/522 , H01L23/5222 , H01L27/11524 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices and methods of fabricating the same are provided. The semiconductor device may include interconnections extending in a first direction on a substrate and spaced apart from each other in a second direction perpendicular to the first direction, barrier dielectric patterns disposed on top surfaces of the interconnections, respectively, and an upper interlayer dielectric layer disposed on the interconnection. Respective air gaps are disposed between adjacent ones of the interconnections.
摘要翻译： 提供半导体器件及其制造方法。 半导体器件可以包括在衬底上沿着第一方向延伸并且在垂直于第一方向的第二方向彼此间隔开的互连，分别设置在互连的顶表面上的势垒电介质图案和布置在 在互连上。 相应的气隙设置在相邻的互连之间。
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公开(公告)号：US20220262819A1
公开(公告)日：2022-08-18
申请号：US17648134
申请日：2022-01-17
发明人： Jeeyong Kim , Junghwan Lee , Hwanyeol Park
IPC分类号： H01L27/11582 , H01L27/11519 , H01L27/11524 , H01L27/11529 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L23/00 , H01L25/065
摘要： An integrated circuit device includes: a semiconductor substrate having a cell region and a dummy region outside the cell region, a plurality of gate electrodes and a plurality of insulating layers, in the cell region, extending in first and second directions parallel to a main surface of the semiconductor substrate and alternately stacked in a third direction perpendicular to the main surface of the semiconductor substrate, the first and second directions crossing each other, and a plurality of dummy mold layers and a plurality of dummy insulating layers alternately stacked in the dummy region in the third direction, wherein a carbon concentration of an upper dummy mold layer of the plurality of dummy mold layers is less than a carbon concentration of a lower dummy mold layer of the plurality of dummy mold layers, the lower dummy mold layer being between the upper dummy mold layer and the main surface of the semiconductor substrate.
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7.发明授权公开(公告)号：US09165820B2
公开(公告)日：2015-10-20
申请号：US14451650
申请日：2014-08-05
发明人： Jeeyong Kim , Hyunchul Back , Jung-Hwan Lee , Hyunmin Lee
IPC分类号： H01L21/768 , H01L23/48 , H01L23/522
CPC分类号： H01L21/7682 , H01L21/76877 , H01L23/481 , H01L23/522 , H01L23/5222 , H01L27/11524 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices and methods of fabricating the same are provided. The semiconductor device may include interconnections extending in a first direction on a substrate and spaced apart from each other in a second direction perpendicular to the first direction, barrier dielectric patterns disposed on top surfaces of the interconnections, respectively, and an upper interlayer dielectric layer disposed on the interconnection. Respective air gaps are disposed between adjacent ones of the interconnections.
摘要翻译： 提供半导体器件及其制造方法。 半导体器件可以包括在衬底上沿着第一方向延伸并且在垂直于第一方向的第二方向彼此间隔开的互连，分别设置在互连的顶表面上的势垒电介质图案和布置在 在互连上。 相应的气隙设置在相邻的互连之间。
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