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公开(公告)号：US12268001B2
公开(公告)日：2025-04-01
申请号：US17736384
申请日：2022-05-04
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jung-Hwan Lee , Hyun Min Cho
Abstract: A nonvolatile memory device with improved reliability is provided. The nonvolatile memory device comprises a substrate, a mold structure including a plurality of word lines stacked on the substrate, a first word line cut region configured to cut the mold structure, a first channel structure spaced apart from the first word line cut region by a first distance, and disposed in the mold structure and the substrate, and a second channel structure spaced apart from the first word line cut region by a second distance, and disposed in the mold structure and the substrate, wherein the second distance is greater than the first distance, a first width of the first channel structure is different from a second width of the second channel structure, and a first length of the first channel structure is different from a second length of the second channel structure.
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2.发明公开公开(公告)号：US20240237341A1
公开(公告)日：2024-07-11
申请号：US18335358
申请日：2023-06-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jung-Hwan Lee , Hyunmin Cho
Abstract: A non-volatile memory device may include a channel structure including a first stacking structure, a second stacking structure, a first channel structure penetrating the first stacking structure, and a second channel structure penetrating the second stacking structure. The second channel structure includes a first portion having a width that decreases or is maintained as the first portion extends toward the substrate, and a second portion having a width that increases as the second portion extends toward the substrate.
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3.发明授权公开(公告)号：US08829682B2
公开(公告)日：2014-09-09
申请号：US13779174
申请日：2013-02-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jeeyong Kim , Hyunchul Back , Jung-Hwan Lee , Hyunmin Lee
IPC: H01L23/48
CPC classification number: H01L21/7682 , H01L21/76877 , H01L23/481 , H01L23/522 , H01L23/5222 , H01L27/11524 , H01L2924/0002 , H01L2924/00
Abstract: Semiconductor devices and methods of fabricating the same are provided. The semiconductor device may include interconnections extending in a first direction on a substrate and spaced apart from each other in a second direction perpendicular to the first direction, barrier dielectric patterns disposed on top surfaces of the interconnections, respectively, and an upper interlayer dielectric layer disposed on the interconnection. Respective air gaps are disposed between adjacent ones of the interconnections.
Abstract translation: 提供半导体器件及其制造方法。 半导体器件可以包括在衬底上沿着第一方向延伸并且在垂直于第一方向的第二方向彼此间隔开的互连，分别设置在互连的顶表面上的势垒电介质图案和布置在 在互连上。 相应的气隙设置在相邻的互连之间。
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4.发明申请Integrated Circuit Devices Including Interconnections Insulated by Air Gaps and Methods of Fabricating the Same 审中-公开包括由空气间隙绝缘的互连的集成电路器件及其制造方法公开(公告)号：US20140342548A1
公开(公告)日：2014-11-20
申请号：US14451650
申请日：2014-08-05
Applicant: Samsung Electronics Co., Ltd
Inventor： Jeeyong Kim , Hyunchul Back , Jung-Hwan Lee , Hyunmin Lee
IPC: H01L21/768
CPC classification number: H01L21/7682 , H01L21/76877 , H01L23/481 , H01L23/522 , H01L23/5222 , H01L27/11524 , H01L2924/0002 , H01L2924/00
Abstract: Semiconductor devices and methods of fabricating the same are provided. The semiconductor device may include interconnections extending in a first direction on a substrate and spaced apart from each other in a second direction perpendicular to the first direction, barrier dielectric patterns disposed on top surfaces of the interconnections, respectively, and an upper interlayer dielectric layer disposed on the interconnection. Respective air gaps are disposed between adjacent ones of the interconnections.
Abstract translation: 提供半导体器件及其制造方法。 半导体器件可以包括在衬底上沿着第一方向延伸并且在垂直于第一方向的第二方向彼此间隔开的互连，分别设置在互连的顶表面上的势垒电介质图案和布置在 在互连上。 相应的气隙设置在相邻的互连之间。
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Patent Agency Ranking
公开(公告)号：US11800708B2
公开(公告)日：2023-10-24
申请号：US16995057
申请日：2020-08-17
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yoo Jin Choi , Jung-Hwan Lee
Abstract: A nonvolatile memory device and method for fabricating the same are provided. The nonvolatile memory device comprising: a substrate; a mold structure including a first insulating pattern and a plurality of gate electrodes alternately stacked in a first direction on the substrate; and a word line cut region which extends in a second direction different from the first direction and cuts the mold structure, wherein the word line cut region includes a common source line, and the common source line includes a second insulating pattern extending in the second direction, and a conductive pattern extending in the second direction and being in contact with the second insulating pattern and a cross-section in the second direction.
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公开(公告)号：US20130260554A1
公开(公告)日：2013-10-03
申请号：US13905375
申请日：2013-05-30
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jeeyong Kim , Woonkyung Lee , Sunggil Kim , Jin-Kyu Kang , Jung-Hwan Lee , Bonyoung Koo , Kihyun Hwang , Byoungsun Ju , Jintae Noh
IPC: H01L21/768 , H01L21/28
CPC classification number: H01L27/11526 , H01L21/28 , H01L21/76841 , H01L23/48 , H01L23/535 , H01L27/11521 , H01L27/11568 , H01L27/11573 , H01L29/4958 , H01L29/78 , H01L29/788 , H01L29/7883 , H01L29/792 , H01L2924/0002 , H01L2924/00
Abstract: Provided are a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a charge storage pattern formed on a substrate; a dielectric pattern formed on the charge storage pattern; a first conductive pattern including silicon doped with a first impurity of a first concentration, the first conductive pattern being disposed on the dielectric pattern; and a second conductive pattern including metal silicide doped with a second impurity of a second concentration, the second conductive pattern being disposed on the first conductive pattern. The first concentration may be higher than the second concentration.
Abstract translation: 提供半导体器件和制造半导体器件的方法。 半导体器件包括形成在衬底上的电荷存储图案; 形成在电荷存储图案上的电介质图案; 第一导电图案，包括掺杂有第一浓度的第一杂质的硅，所述第一导电图案设置在所述电介质图案上; 以及第二导电图案，其包括掺杂有第二浓度的第二杂质的金属硅化物，所述第二导电图案设置在所述第一导电图案上。 第一浓度可能高于第二浓度。
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7.发明授权公开(公告)号：US09165820B2
公开(公告)日：2015-10-20
申请号：US14451650
申请日：2014-08-05
Applicant: Samsung Electronics Co., Ltd
Inventor： Jeeyong Kim , Hyunchul Back , Jung-Hwan Lee , Hyunmin Lee
IPC: H01L21/768 , H01L23/48 , H01L23/522
CPC classification number: H01L21/7682 , H01L21/76877 , H01L23/481 , H01L23/522 , H01L23/5222 , H01L27/11524 , H01L2924/0002 , H01L2924/00
Abstract: Semiconductor devices and methods of fabricating the same are provided. The semiconductor device may include interconnections extending in a first direction on a substrate and spaced apart from each other in a second direction perpendicular to the first direction, barrier dielectric patterns disposed on top surfaces of the interconnections, respectively, and an upper interlayer dielectric layer disposed on the interconnection. Respective air gaps are disposed between adjacent ones of the interconnections.
Abstract translation: 提供半导体器件及其制造方法。 半导体器件可以包括在衬底上沿着第一方向延伸并且在垂直于第一方向的第二方向彼此间隔开的互连，分别设置在互连的顶表面上的势垒电介质图案和布置在 在互连上。 相应的气隙设置在相邻的互连之间。
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8.发明申请INTEGRATED CIRCUIT DEVICES INCLUDING INTERCONNECTIONS INSULATED BY AIR GAPS AND METHODS OF FABRICATING THE SAME 有权集成电路设备，包括由空气保险丝绝缘的互连及其制造方法公开(公告)号：US20130228934A1
公开(公告)日：2013-09-05
申请号：US13779174
申请日：2013-02-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jeeyong KIM , Hyunchul Back , Jung-Hwan Lee , Hyunmin Lee
IPC: H01L23/48
CPC classification number: H01L21/7682 , H01L21/76877 , H01L23/481 , H01L23/522 , H01L23/5222 , H01L27/11524 , H01L2924/0002 , H01L2924/00
Abstract: Semiconductor devices and methods of fabricating the same are provided. The semiconductor device may include interconnections extending in a first direction on a substrate and spaced apart from each other in a second direction perpendicular to the first direction, barrier dielectric patterns disposed on top surfaces of the interconnections, respectively, and an upper interlayer dielectric layer disposed on the interconnection. Respective air gaps are disposed between adjacent ones of the interconnections.
Abstract translation: 提供半导体器件及其制造方法。 半导体器件可以包括在衬底上沿着第一方向延伸并且在垂直于第一方向的第二方向彼此间隔开的互连，分别设置在互连的顶表面上的势垒电介质图案和布置在 在互连上。 相应的气隙设置在相邻的互连之间。
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公开(公告)号：US20230010192A1
公开(公告)日：2023-01-12
申请号：US17702400
申请日：2022-03-23
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jung-Hwan Lee , Jin-Soo Lim
IPC: H01L23/544 , H01L27/11556 , H01L27/11529 , H01L27/11582 , H01L27/11573
Abstract: A non-volatile memory device and a non-volatile memory system comprising the same are provided. The non-volatile memory device includes a first stack in which a first conductive pattern and a first dielectric layer are alternately stacked in a first direction on a substrate, a second stack in which a second conductive pattern and a second dielectric layer are alternately stacked in the first direction on the first stack opposite the substrate, a first monitoring channel structure that penetrates the first stack in the first direction, and a second monitoring channel structure that penetrates the second stack in the first direction and is =on the first monitoring channel structure. A width of a top of the first monitoring channel structure opposite the substrate is smaller than a width of a bottom of the second monitoring channel structure adjacent the top of the first monitoring channel structure.
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