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公开(公告)号：US20240038292A1
公开(公告)日：2024-02-01
申请号：US18357204
申请日：2023-07-24
发明人： Kiheung Kim , Taeyoung Oh , Jongcheol Kim , Kyungho Lee , Hyongryol Hwang
IPC分类号： G11C11/4078 , G11C11/4096 , G11C11/4076 , G11C11/406
CPC分类号： G11C11/4078 , G11C11/4096 , G11C11/4076 , G11C11/40622
摘要： A semiconductor memory device includes a memory cell array including a plurality of memory cell rows, a row hammer management circuit and a control logic circuit. The row hammer management circuit stores counted values in count cells of each of the plurality of memory cell rows as count data based on an active command applied to the control logic circuit at a first time point, and performs an internal read-update-write operation to read the count data from the count cells of a target memory cell row from among the plurality of memory cell rows, to update the count data that was read to obtain updated count data, and to write the updated count data in the count cells of the target memory cell row in response to a precharge command applied at a second time point after a first command that is applied to the control logic circuit.
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公开(公告)号：US20230418487A1
公开(公告)日：2023-12-28
申请号：US18136915
申请日：2023-04-20
发明人： Jongcheol Kim , Kiheung Kim , Taeyoung Oh , Kyungho Lee
IPC分类号： G06F3/06
CPC分类号： G06F3/0632 , G06F3/0604 , G06F3/0679
摘要： A semiconductor memory device includes a memory cell array, a row hammer management circuit and a refresh control circuit. The row hammer management circuit automatically stores random count data in count cells of each of a plurality of memory cell rows during a power-up sequence of the semiconductor memory device and determines counted values by counting a number of times of access associated with each of the plurality of memory cell rows in response to an active command from an external memory controller and stores the counted values in the count cells of each of the plurality of memory cell rows as count data. The refresh control circuit receives a hammer address and performs a hammer refresh operation on one or more of the plurality of memory cell rows that are physically adjacent to a memory cell row that corresponds to the hammer address.
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公开(公告)号：US20230342050A1
公开(公告)日：2023-10-26
申请号：US18304813
申请日：2023-04-21
发明人： Youngdo Um , Taeyoung Oh , Hoseok Seol
IPC分类号： G06F3/06
CPC分类号： G06F3/0634 , G06F3/0611 , G06F3/0673
摘要： Provided is a memory system including a host system including a memory controller configured to control a read or write operation for a plurality of memory ranks, based on target or non-target information for the plurality of memory ranks, and a memory device including a storage configured to store on-die termination (ODT) information of the memory ranks. Here, the memory controller is further configured to determine a target rank to be read or written, and transmit information about the determined target rank, to the memory device, and the memory device is further configured to perform a comparison of the ODT information of the memory ranks stored in the storage with target or non-target information received from the memory controller, and change an ODT value of the target rank, based on target information received from the memory controller based on a result of the comparison.
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公开(公告)号：US10242719B2
公开(公告)日：2019-03-26
申请号：US15416140
申请日：2017-01-26
发明人： Su Yeon Doo , Taeyoung Oh
IPC分类号： G06F1/00 , G11C5/14 , G06F1/26 , G06F1/3287 , G06F1/3296
摘要： An electronic device includes a memory device including a power switch configured to provide one of a first voltage and a second voltage to an internal circuit in response to a control command. A power management device is configured to generate the first voltage, the second voltage, and the control command and to provide the first voltage, the second voltage, and the control command to the memory device. The power switch provides the second voltage to the internal circuit while a level of the first voltage is changed and provides the first voltage to the internal circuit after a level change of the first voltage is completed.
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公开(公告)号：US12118221B2
公开(公告)日：2024-10-15
申请号：US18136915
申请日：2023-04-20
发明人： Jongcheol Kim , Kiheung Kim , Taeyoung Oh , Kyungho Lee
CPC分类号： G06F3/0632 , G06F3/0604 , G06F3/0679
摘要： A semiconductor memory device includes a memory cell array, a row hammer management circuit and a refresh control circuit. The row hammer management circuit automatically stores random count data in count cells of each of a plurality of memory cell rows during a power-up sequence of the semiconductor memory device and determines counted values by counting a number of times of access associated with each of the plurality of memory cell rows in response to an active command from an external memory controller and stores the counted values in the count cells of each of the plurality of memory cell rows as count data. The refresh control circuit receives a hammer address and performs a hammer refresh operation on one or more of the plurality of memory cell rows that are physically adjacent to a memory cell row that corresponds to the hammer address.
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6.发明公开公开(公告)号：US20240289058A1
公开(公告)日：2024-08-29
申请号：US18590324
申请日：2024-02-28
发明人： Ki-Heung KIM , Taeyoung Oh , Taekwoon Kim , Jinseong Yun , Yoonjae Jeong , Hyongryol Hwang
IPC分类号： G06F3/06
CPC分类号： G06F3/0659 , G06F3/0604 , G06F3/0683
摘要： A method of operating a memory module that communicates with a memory controller includes: entering a one-time programmable (OTP) addressing mode based on an OTP command received from the memory controller; determining whether a guard key sequence is satisfied based on a plurality of mode register commands received from the memory controller; and programming, based on a determination that the guard key sequence is satisfied, a unique identifier (ID), corresponding to a target memory device, into the target memory device, among a plurality of memory devices included in the memory module.
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公开(公告)号：US20240220149A1
公开(公告)日：2024-07-04
申请号：US18243268
申请日：2023-09-07
发明人： Kiheung Kim , Taeyoung Oh
IPC分类号： G06F3/06
CPC分类号： G06F3/0655 , G06F3/0604 , G06F3/064 , G06F3/0673
摘要： A semiconductor memory device includes a memory cell array and a column access circuit. The memory cell array includes a plurality of sub-array blocks and each of the sub-array blocks includes volatile memory cells. The column access circuit receives a plurality of data units, each of which includes normal data and meta data having a ratio of k:1, which is associated with managing the normal data, allocates p column selection lines associated with transferring the data units to the bit-lines to a plurality of normal data and a plurality of meta data in the data units with the ratio of k:1, and stores a sub unit of a first normal data among the plurality of normal data and a sub unit of a first meta data in a first region and a second region of a first sub-array block of the plurality of sub-array blocks, respectively.
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公开(公告)号：US20230185460A1
公开(公告)日：2023-06-15
申请号：US18076628
申请日：2022-12-07
发明人： Kiheung Kim , Taeyoung Oh , Hyeran Kim , Sungyong Cho , Kyungsoo Ha
IPC分类号： G06F3/06
CPC分类号： G06F3/0619 , G06F3/0653 , G06F3/0659 , G06F3/0673
摘要： A semiconductor memory device includes a memory cell array, a row hammer management circuit and a control logic circuit. The memory cell array includes a plurality of memory cell rows. The row hammer management circuit counts the number of instances of access of each of the memory cell rows, such as in response to the receipt of an active command, to store the counted values in count cells of each of the memory cell rows as count data and, in response to a first command, initiates an internal read-update-write operation to read the count data, to update the read count data, and to write the updated count data in the count cells. The control logic circuit may performs an internal write operation to write the updated count data in the count cells during a second write time interval that is smaller than a first write time interval associated with a normal write operation.
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公开(公告)号：US10665558B2
公开(公告)日：2020-05-26
申请号：US16036198
申请日：2018-07-16
发明人： Sihong Kim , Young-Hoon Son , Taeyoung Oh , Kyung-Soo Ha
摘要： A semiconductor memory includes a plurality of first pads arranged in a first direction, a plurality of second pads arranged parallel to the plurality of first pads and in the first direction, a plurality of third pads arranged in a second direction perpendicular to the first direction, and a plurality of fourth pads arranged in the second direction. The semiconductor memory further includes first interconnection wires extending from the plurality of first pads in the second direction, the first interconnection wires being connected to the plurality of third pads, and second interconnection wires extending from the plurality of second pads in an opposite direction to the second direction, the second interconnection wires being connected to the plurality of fourth pads.
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公开(公告)号：US12080334B2
公开(公告)日：2024-09-03
申请号：US17885081
申请日：2022-08-10
发明人： Taeyoung Oh
IPC分类号： G11C11/40 , G11C11/406 , G11C11/4096
CPC分类号： G11C11/40618 , G11C11/40611 , G11C11/4096
摘要： A semiconductor memory device includes a row hammer management circuit and a refresh control circuit. The row hammer management circuit counts the number of times of access on each memory cell row to store the counted values in count cells of each memory cell row as count data. A hammer address queue in the row hammer management circuit stores candidate hammer addresses, which are intensively accessed, in response to a number of the candidate hammer addresses reaching a second number, transitions a logic level of an error signal provided to the memory controller, and, in response to the number of the candidate hammer addresses reaching the first number, outputs one of the candidate hammer addresses as a hammer address. The refresh control circuit performs a hammer refresh operation on victim memory cell rows which are physically adjacent to a memory cell row corresponding to the hammer address.
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