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公开(公告)号：US20170345507A1
公开(公告)日：2017-11-30
申请号：US15680104
申请日：2017-08-17
发明人： Jong-Chul PARK , Seung-Bum KIM , Myung-Hoon CHOI
CPC分类号： G11C16/14 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/3445 , G11C16/3459 , G11C16/3477
摘要： A nonvolatile memory device includes a memory cell array having memory cells, a row decoder circuit connected to the memory cells through word lines, a page buffer circuit connected to the memory cells through bit lines, and a control circuit controlling the row decoder circuit and the page buffer circuit to repeatedly perform an erase loop including an erase and an erase verification with respect to the memory cells. The control circuit is configured to select one of an increase and a decrease of an erase voltage according to a result of the erase verification of a current erase loop and apply the controlled erase voltage to the memory cells in the erase operation of a subsequent erase loop.
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2.发明申请公开(公告)号：US20200293204A1
公开(公告)日：2020-09-17
申请号：US16892512
申请日：2020-06-04
发明人： Seung-Bum KIM
IPC分类号： G06F3/06 , G11C16/30 , G11C5/14 , H01L27/1157 , H01L27/11565 , G06F11/10 , G11C11/56 , G11C16/04 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/26 , G11C29/52
摘要： Nonvolatile memory device includes a memory cell array and a control circuit. The memory cell array includes a plurality of memory blocks, the memory blocks including a plurality of memory cells coupled to word-lines respectively, the word-lines are stacked vertically on a substrate, and some memory cells of the plurality of memory cells are selected by sub-block unit smaller than one memory block. The control circuit divides sub-blocks of a first memory block into at least one bad sub-block and at least one normal sub-block based on error occurrence frequency of each of the sub-blocks, and applies different program/erase cycles to the at least one bad sub-block and the at least one normal sub-block based on a command and an address provided from external to the nonvolatile memory device. The at least one bad sub-block and the at least one normal sub-block are adjacent each other.
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3.发明申请公开(公告)号：US20190196744A1
公开(公告)日：2019-06-27
申请号：US16111813
申请日：2018-08-24
发明人： Seung-Bum KIM
IPC分类号： G06F3/06 , G11C16/10 , G11C16/14 , G11C16/08 , G11C11/56 , G11C16/26 , G11C16/04 , G06F11/10 , G11C29/52
摘要： Nonvolatile memory device includes a memory cell array and a control circuit. The memory cell array includes a plurality of memory blocks, the memory blocks including a plurality of memory cells coupled to word-lines respectively, the word-lines are stacked vertically on a substrate, and some memory cells of the plurality of memory cells are selected by sub-block unit smaller than one memory block. The control circuit divides sub-blocks of a first memory block into at least one bad sub-block and at least one normal sub-block based on error occurrence frequency of each of the sub-blocks, and applies different program/erase cycles to the at least one bad sub-block and the at least one normal sub-block based on a command and an address provided from external to the nonvolatile memory device. The at least one bad sub-block and the at least one normal sub-block are adjacent each other.
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4.发明申请NONVOLATILE MEMORY DEVICES, MEMORY SYSTEMS AND METHODS OF PERFORMING READ OPERATIONS 有权非易失性存储器件，存储器系统和执行读操作的方法公开(公告)号：US20140036593A1
公开(公告)日：2014-02-06
申请号：US14048944
申请日：2013-10-08
发明人： Seung-Bum KIM
IPC分类号： G11C16/26
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/0483
摘要： Within a non-volatile memory device, a read operation directed to a nonvolatile memory cell having a positive threshold voltage applies a positive read voltage to a selected word line and a first control signal to a page buffer connected to a selected bit line, but if the memory cell has a negative threshold voltage the read operation applies a negative read voltage to the selected word line and a second control signal to the page buffer different from the first control signal.
摘要翻译： 在非易失性存储器件中，针对具有正阈值电压的非易失性存储单元的读取操作将正读取电压施加到所选字线和第一控制信号到连接到所选位线的页缓冲器，但如果 存储单元具有负的阈值电压，读取操作将一个负的读取电压施加到所选择的字线，并且将第二个控制信号施加到与第一个控制信号不同的页面缓冲器。
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公开(公告)号：US20130219109A1
公开(公告)日：2013-08-22
申请号：US13755144
申请日：2013-01-31
发明人： Seung-Bum KIM , Jaeyong JEONG , Kitae PARK
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F11/1068 , G11C7/1006 , G11C11/5628 , G11C16/10 , G11C2211/5641
摘要： A memory system includes a nonvolatile memory device having a first data area storing M-bit data using a buffer program operation and a second data area storing N-bit data (N being an integer larger than M) using a main program operation and a memory controller configured to control the nonvolatile memory device. When a main program operation using data stored at the first and second data areas is required, the memory controller calculates values indicating a performance of the required main program operation to be executed according to a plurality of main program manners, selects one of the plurality of main program manners based on the calculated values, and controls the nonvolatile memory device to perform the required main program operation according to the selected main program manner.
摘要翻译： 存储器系统包括：非易失性存储器件，其具有使用缓冲器程序操作存储M位数据的第一数据区和使用主程序操作存储N位数据（N大于M的整数）的第二数据区;存储器 控制器被配置为控制非易失性存储器件。 当需要使用存储在第一和第二数据区域的数据的主程序操作时，存储器控制器根据多个主程序方式计算指示要执行的所需主程序操作的性能的值，选择多个 基于计算值的主程序方式，并且根据选择的主程序方式控制非易失性存储器件执行所需的主程序操作。
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公开(公告)号：US20210011633A1
公开(公告)日：2021-01-14
申请号：US17033077
申请日：2020-09-25
发明人： Seung-Bum KIM
IPC分类号： G06F3/06 , G11C16/30 , G11C5/14 , H01L27/1157 , H01L27/11565 , G06F11/10 , G11C11/56 , G11C16/04 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/26 , G11C29/52
摘要： A nonvolatile memory device includes a memory cell region having a first metal pad and a peripheral circuit region having a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad, a a memory cell array in the memory cell region and an address decoder in the peripheral circuit region. The memory cell array includes memory blocks, and each memory block includes memory cells coupled to word-lines respectively. The word-lines are stacked vertically on a substrate, and some memory cells of the plurality of memory cells are selectable by a sub-block unit smaller than one memory block of the plurality of memory blocks. The address decoder applies an erase voltage to each of sub-blocks in a first memory block of the plurality of memory blocks through the first metal pad and the second metal pad.
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公开(公告)号：US20210005268A1
公开(公告)日：2021-01-07
申请号：US17023556
申请日：2020-09-17
发明人： Seung-Bum KIM , Il-Han PARK , Ji-Young LEE , Su-Chang JEON
摘要： Nonvolatile memory device includes memory cell region including a first metal pad and a second metal pad, peripheral circuit region including a third metal pad and a fourth metal pad, vertically connected to the memory cell region. The nonvolatile memory device includes a page buffer circuit including page buffers to sense data from selected memory cells, each including two sequential sensing operations to determine one data state, and each of the page buffers including a latch to sequentially store results of the two sequential sensing operations. The nonvolatile memory device includes control circuit in the peripheral circuit region, to control the page buffers to store result of the first read operation, reset the latches after completion of the first read operation, and control the page buffers to perform the second read operation based on a valley determined based on the result of the first read operation.
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