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    NONVOLATILE MEMORY DEVICE AND METHOD OF PERFORMING AN ERASE OPERATION IN THE SAME
    1.
    发明申请
    NONVOLATILE MEMORY DEVICE AND METHOD OF PERFORMING AN ERASE OPERATION IN THE SAME 审中-公开

    公开(公告)号：US20190221267A1

    公开(公告)日：2019-07-18

    申请号：US16176117

    申请日：2018-10-31

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kui-Han KO ,  Jin-Young KIM ,  Bong-Soon LIM ,  Il-Han PARK

    IPC: G11C16/16 ,  G11C16/04

    CPC classification number: G11C16/16 ,  G11C16/0483 ,  H01L27/11556

    Abstract: An erase voltage is applied to channels of a selected string group to erase only the selected string group. A size and a number of the spare blocks for storing meta data are reduced and thus a size of the nonvolatile memory device is reduced by reducing unit capacity of the erase operation through grouping of the cell strings. Lifetime of the nonvolatile memory device is extended by having control over erasing some cell strings and not others. Control of cell strings for erasure includes allowing some control lines to float, in some embodiments. In some embodiments, ground select transistors with different thresholds and appropriately applied voltages are used to control erasure of particular cell strings. In some embodiments, biasing of word lines is applied differently to portions of a particular cell string to only erase a portion of the particular cell string.

    NONVOLATILE MEMORY DEVICE WITH CAPABILITY OF DETERMINING DEGRADATION OF DATA ERASE CHARACTERISTICS
    2.
    发明申请
    NONVOLATILE MEMORY DEVICE WITH CAPABILITY OF DETERMINING DEGRADATION OF DATA ERASE CHARACTERISTICS 有权

    公开(公告)号：US20220199174A1

    公开(公告)日：2022-06-23

    申请号：US17694229

    申请日：2022-03-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seong-Jin SONG ,  Hyun-Wook PARK ,  Bong-Soon LIM ,  Do-Bin KIM

    IPC: G11C16/34 ,  G11C16/04 ,  G11C16/14 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

    Abstract: A nonvolatile memory device includes a memory cell region and a peripheral circuit region. The memory cell region includes a memory block, and the peripheral circuit region includes a control circuit. The memory cell region includes a first metal pad. The peripheral circuit region includes a second metal pad and is vertically connected to the memory cell region by the first metal pad and the second metal pad. The memory block includes a plurality of memory cells disposed in a vertical direction. The control circuit determines whether a data erase characteristic for the memory block is degraded for each predetermined cycle of data erase operation, and performs a data erase operation by changing a level of a voltage applied to selection transistors for selecting the memory block as an erase target block when it is determined that the data erase characteristic is degraded.

    NONVOLATILE MEMORY DEVICE, VERTICAL NAND FLASH MEMORY DEVICE AND SSD DEVICE INCLUDING THE SAME
    3.
    发明申请
    NONVOLATILE MEMORY DEVICE, VERTICAL NAND FLASH MEMORY DEVICE AND SSD DEVICE INCLUDING THE SAME 审中-公开

    公开(公告)号：US20200135758A1

    公开(公告)日：2020-04-30

    申请号：US16440299

    申请日：2019-06-13

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sang-Won PARK ,  Sang-Wan NAM ,  Bong-Soon LIM

    IPC: H01L27/11582 ,  G11C16/04 ,  G11C16/14 ,  G11C16/10 ,  G11C16/26 ,  H01L27/1157 ,  H01L27/11573 ,  G06F3/06

    Abstract: A nonvolatile memory device includes a semiconductor substrate including a page buffer region, a memory cell array, bitlines, first vertical conduction paths, and second vertical conduction paths. The memory cell array is formed in a memory cell region above the semiconductor substrate and includes memory cells. The bitlines extend in a column direction above the memory cell array. Each of bitlines is cut into each of first bitline segments and each of second bitline segments. The first vertical conduction paths extend in a vertical direction and penetrate a column-directional central region of the memory cell region. The first vertical conduction paths connect the first bitline segments and the page buffer region. The second vertical conduction paths extend in the vertical direction and penetrate the column-directional central region. The second vertical conduction paths connect the second bitline segments and the page buffer region.

    NONVOLATILE MEMORY DEVICE WITH INTERMEDIATE SWITCHING TRANSISTORS AND PROGRAMMING METHOD
    4.
    发明申请
    NONVOLATILE MEMORY DEVICE WITH INTERMEDIATE SWITCHING TRANSISTORS AND PROGRAMMING METHOD 有权

    公开(公告)号：US20220036954A1

    公开(公告)日：2022-02-03

    申请号：US17503952

    申请日：2021-10-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Chang-Yeon YU ,  Kui-Han KO ,  Il-Han PARK ,  June-Hong PARK ,  Joo-Yong PARK ,  Joon-Young PARK ,  Bong-Soon LIM

    IPC: G11C16/10 ,  G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24

    Abstract: To program in a nonvolatile memory device including a cell region including first metal pads and a peripheral region including second metal pads and vertically connected to the cell region by the first metal pads and the second metal pads, a memory block is provided with a plurality of sub blocks disposed in a vertical direction where the memory block includes a plurality of cell strings each including a plurality of memory cells connected in series and disposed in the vertical direction. A plurality of intermediate switching transistors are disposed in a boundary portion between two adjacent sub blocks in the vertical direction. Each of the plurality of intermediate switching transistors is selectively activated based on a program address during a program operation. The selectively activating each of the plurality of intermediate switching transistors includes selectively turning on one or more intermediate switching transistors in a selected cell string based on the program address.

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