公开(公告)号：US10056466B2

公开(公告)日：2018-08-21

申请号：US15191555

申请日：2016-06-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-Jae Lee ,  Ja-Eung Koo ,  Ho-Young Kim ,  Yeong-Bong Park ,  Il-Su Park ,  Bo-Un Yoon ,  Il-Young Yoon ,  Youn-Su Ha

IPC: H01L29/66 ,  H01L21/321 ,  H01L21/3105 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/66545 ,  H01L21/31051 ,  H01L21/3212 ,  H01L21/823437 ,  H01L21/82345 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/517

Abstract: A method for fabricating a semiconductor device may comprise forming a first transistor having a first threshold voltage in a first region of a substrate, forming a second transistor having a second threshold voltage less than the first threshold voltage in a second region of the substrate, forming a third interlayer insulating film in the third region, and planarizing the first transistor, the second transistor and the third interlayer insulating film. The first transistor may include a first gate electrode having a first height and a first interlayer insulating film having the first height, and the second transistor may include a second gate electrode having a second height shorter than the first height and a second interlayer insulating film having the second height. The third interlayer insulating film may have the first height.

公开(公告)号：US10910266B2

公开(公告)日：2021-02-02

申请号：US16295751

申请日：2019-03-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Hoon Choi ,  Ja-Eung Koo ,  Kwan-Sik Kim ,  Dong-Chan Kim ,  Il-Young Yoon ,  Man-Geun Cho

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/48 ,  H01L23/528 ,  H01L27/30 ,  H01L27/146 ,  H01L21/321

Abstract: A method of manufacturing a semiconductor device includes forming a via including a first conductive material on an inner wall of a trench on a substrate. The method further includes forming a first insulating interlayer on the substrate. The first insulating interlayer covers the via and partially fills the trench, and the first insulating interlayer has a non-flat upper surface. The method further includes forming a polishing stop layer on the first insulating interlayer, forming a second insulating interlayer on the polishing stop layer, in which the second insulating interlayer fills a remaining portion of the trench, planarizing the second insulating interlayer until the polishing stop layer is exposed, and etching the polishing stop layer and the first and second insulating interlayers using a dry etching process until remaining portions of the polishing stop layer except for a portion of the polishing stop layer in the trench are removed.

公开(公告)号：US09023704B2

公开(公告)日：2015-05-05

申请号：US13801341

申请日：2013-03-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Il-Young Yoon ,  Chang-Sun Hwang ,  Bo-Kyeong Kang ,  Jae-Seok Kim ,  Ho-Young Kim ,  Bo-Un Yoon

IPC: H01L21/336 ,  H01L27/14 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L29/66545

Abstract: A method for fabricating a semiconductor device includes forming a pre-isolation layer covering a fin formed on a substrate, the pre-isolation layer including a lower pre-isolation layer making contact with the fin and an upper pre-isolation layer not making contact with the fin, removing a portion of the upper pre-isolation layer by performing a first polishing process, and planarizing the pre-isolation layer such that an upper surface of the fin and an upper surface of the pre-isolation layer are coplanar by performing a second polishing process for removing the remaining portion of the upper pre-isolation layer.

Abstract translation: 一种制造半导体器件的方法包括形成覆盖形成在衬底上的翅片的预隔离层，所述预隔离层包括与所述翅片接触的下预分离层和不与所述翅片接触的上预隔离层 通过执行第一抛光工艺去除上部预隔离层的一部分，并且平坦化预隔离层，使得翅片的上表面和预隔离层的上表面共面，通过执行 用于去除上部预隔离层的剩余部分的第二抛光工艺。

公开(公告)号：US11361995B2

公开(公告)日：2022-06-14

申请号：US17146597

申请日：2021-01-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Hoon Choi ,  Ja-Eung Koo ,  Kwan-Sik Kim ,  Dong-Chan Kim ,  Il-Young Yoon ,  Man-Geun Cho

IPC: H01L21/768 ,  H01L21/321 ,  H01L27/146 ,  H01L23/52 ,  H01L23/522 ,  H01L23/528 ,  H01L23/48 ,  H01L27/30

Abstract: A method of manufacturing a semiconductor device includes forming a via including a first conductive material on an inner wall of a trench on a substrate. The method further includes forming a first insulating interlayer on the substrate. The first insulating interlayer covers the via and partially fills the trench, and the first insulating interlayer has a non-flat upper surface. The method further includes forming a polishing stop layer on the first insulating interlayer, forming a second insulating interlayer on the polishing stop layer, in which the second insulating interlayer fills a remaining portion of the trench, planarizing the second insulating interlayer until the polishing stop layer is exposed, and etching the polishing stop layer and the first and second insulating interlayers using a dry etching process until remaining portions of the polishing stop layer except for a portion of the polishing stop layer in the trench are removed.

公开(公告)号：US20210166976A1

公开(公告)日：2021-06-03

申请号：US17146597

申请日：2021-01-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Hoon Choi ,  Ja-Eung Koo ,  Kwan-Sik Kim ,  Dong-Chan Kim ,  Il-Young Yoon ,  Man-Geun Cho

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/48 ,  H01L27/30 ,  H01L21/321

Abstract: A method of manufacturing a semiconductor device includes forming a via including a first conductive material on an inner wall of a trench on a substrate. The method further includes forming a first insulating interlayer on the substrate. The first insulating interlayer covers the via and partially fills the trench, and the first insulating interlayer has a non-flat upper surface. The method further includes forming a polishing stop layer on the first insulating interlayer, forming a second insulating interlayer on the polishing stop layer, in which the second insulating interlayer fills a remaining portion of the trench, planarizing the second insulating interlayer until the polishing stop layer is exposed, and etching the polishing stop layer and the first and second insulating interlayers using a dry etching process until remaining portions of the polishing stop layer except for a portion of the polishing stop layer in the trench are removed.