公开(公告)号：US20170345825A1

公开(公告)日：2017-11-30

申请号：US15680960

申请日：2017-08-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Jine Park ,  Kee-Sang Kwon ,  Do-Hyoung Kim ,  Bo-Un Yoon ,  Keun-Hee Bai ,  Kwang-Yong Yang ,  Kyoung-Hwan Yeo ,  Yong-Ho Jeon

IPC: H01L27/11 ,  H01L29/165 ,  H01L29/161 ,  H01L29/16 ,  H01L21/8234 ,  H01L29/06 ,  H01L21/762 ,  H01L27/092 ,  H01L27/088 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L27/1104 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1116 ,  H01L29/06 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7848

Abstract: Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.

公开(公告)号：US20170271336A1

公开(公告)日：2017-09-21

申请号：US15616455

申请日：2017-06-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Jine Park ,  Bo-Un Yoon ,  Ha-Young Jeon ,  Yeon-Jin Gil ,  Ji-Won Yun ,  Won-Sang Choi

IPC: H01L27/092 ,  H01L27/088 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/165

CPC classification number: H01L27/0924 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L29/165 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/785

Abstract: Semiconductor devices are provided. A semiconductor device includes a fin protruding from a substrate. Moreover, the semiconductor device includes first and second gate structures on the fin, and an isolation region between the first and second gate structures. The isolation region includes first and second portions having different respective widths. Related methods of forming semiconductor devices are also provided.

公开(公告)号：US09590073B2

公开(公告)日：2017-03-07

申请号：US14815225

申请日：2015-07-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeon-Tack Ryu ,  Ho-Young Kim ,  Myoung-Hwan Oh ,  Bo-Un Yoon ,  Jun-Hwan Yim

IPC: H01L21/00 ,  H01L29/66 ,  H01L29/49 ,  H01L29/51 ,  H01L21/8234 ,  H01L21/768

CPC classification number: H01L29/66545 ,  H01L21/31053 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76897 ,  H01L21/823437 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

Abstract: Semiconductor devices and methods of fabricating semiconductor devices are provided. The methods may include forming an interlayer insulation layer on a substrate. The interlayer insulation layer may surround a dummy silicon gate and may expose a top surface of the dummy silicon gate. The methods may also include recessing a portion of the interlayer insulation layer such that a portion of the dummy silicon gate protrudes above a top surface of the recessed interlayer insulation layer and forming an etch stop layer on the recessed interlayer insulation layer. A top surface of the etch stop layer may be coplanarly positioned with the top surface of the dummy silicon gate. The methods may further include forming a trench exposing the substrate by removing the dummy silicon gate using the etch stop layer as a mask.

Abstract translation: 提供了制造半导体器件的半导体器件和方法。 所述方法可以包括在基底上形成层间绝缘层。 层间绝缘层可以包围虚拟硅栅极并且可以暴露虚拟硅栅极的顶表面。 所述方法还可以包括使所述层间绝缘层的一部分凹陷，使得所述虚拟硅栅极的一部分突出于所述凹陷层间绝缘层的顶表面之上，并在所述凹陷层间绝缘层上形成蚀刻停止层。 蚀刻停止层的顶表面可以与虚拟硅栅极的顶表面共面定位。 所述方法还可以包括通过使用蚀刻停止层作为掩模去除伪硅栅极来形成暴露衬底的沟槽。

公开(公告)号：US08796107B2

公开(公告)日：2014-08-05

申请号：US13679345

申请日：2012-11-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kevin Ahn ,  Bo-Un Yoon ,  Jeong-Nam Han

IPC: H01L21/762 ,  H01L21/311 ,  H01L21/336 ,  H01L21/02 ,  H01L21/306 ,  H01L29/66 ,  H01L21/04

CPC classification number: H01L21/76229 ,  H01L21/0206 ,  H01L21/02065 ,  H01L21/0475 ,  H01L21/30604 ,  H01L21/30621 ,  H01L21/31055 ,  H01L21/31056 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76205 ,  H01L21/823468 ,  H01L21/823481 ,  H01L29/66545

Abstract: Provided are methods for fabricating a semiconductor device. The methods include forming a hard mask pattern on a semiconductor substrate, forming a first trench having a first width and a second trench having a second width on the semiconductor substrate using the hard mask pattern as a mask, forming an oxide film on the hard mask pattern and the first and second trenches, forming first and second isolation films on the first and second trenches by planarizing the oxide film until the hard mask pattern is exposed, and etching the first isolation film by a first thickness by performing dry cleaning on the semiconductor substrate and etching the second isolation film by a second thickness different from the first thickness.

Abstract translation: 提供了制造半导体器件的方法。 所述方法包括在半导体衬底上形成硬掩模图案，使用硬掩模图案作为掩模，在半导体衬底上形成具有第一宽度的第一沟槽和具有第二宽度的第二沟槽，在硬掩模上形成氧化物膜 图案和第一沟槽和第二沟槽，通过平坦化氧化膜直到硬掩模图案露出来在第一和第二沟槽上形成第一和第二隔离膜，并且通过对半导体进行干洗来蚀刻第一隔离膜第一厚度第一厚度 衬底并用不同于第一厚度的第二厚度蚀刻第二隔离膜。

公开(公告)号：US10192973B2

公开(公告)日：2019-01-29

申请号：US15239200

申请日：2016-08-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Jine Park ,  Bo-Un Yoon ,  Ha-Young Jeon ,  Byung-Kwon Cho ,  Jeong-Nam Han

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/28 ,  H01L29/49 ,  H01L27/088 ,  H01L29/423

Abstract: A semiconductor device includes a gate spacer defining a trench. The trench includes a first part and a second part sequentially positioned on a substrate. An inner surface of the first part has a slope of an acute angle and an inner surface of the second part has a slope of a right angle or obtuse angle with respect to the substrate. A gate electrode fills at least a portion of the trench.

公开(公告)号：US10128246B2

公开(公告)日：2018-11-13

申请号：US15616455

申请日：2017-06-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Jine Park ,  Bo-Un Yoon ,  Ha-Young Jeon ,  Yeon-Jin Gil ,  Ji-Won Yun ,  Won-Sang Choi

IPC: H01L21/70 ,  H01L27/092 ,  H01L29/78 ,  H01L27/088 ,  H01L21/762 ,  H01L29/165 ,  H01L21/8238

Abstract: Semiconductor devices are provided. A semiconductor device includes a fin protruding from a substrate. Moreover, the semiconductor device includes first and second gate structures on the fin, and an isolation region between the first and second gate structures. The isolation region includes first and second portions having different respective widths. Related methods of forming semiconductor devices are also provided.

公开(公告)号：US10056466B2

公开(公告)日：2018-08-21

申请号：US15191555

申请日：2016-06-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-Jae Lee ,  Ja-Eung Koo ,  Ho-Young Kim ,  Yeong-Bong Park ,  Il-Su Park ,  Bo-Un Yoon ,  Il-Young Yoon ,  Youn-Su Ha

IPC: H01L29/66 ,  H01L21/321 ,  H01L21/3105 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/66545 ,  H01L21/31051 ,  H01L21/3212 ,  H01L21/823437 ,  H01L21/82345 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/517

Abstract: A method for fabricating a semiconductor device may comprise forming a first transistor having a first threshold voltage in a first region of a substrate, forming a second transistor having a second threshold voltage less than the first threshold voltage in a second region of the substrate, forming a third interlayer insulating film in the third region, and planarizing the first transistor, the second transistor and the third interlayer insulating film. The first transistor may include a first gate electrode having a first height and a first interlayer insulating film having the first height, and the second transistor may include a second gate electrode having a second height shorter than the first height and a second interlayer insulating film having the second height. The third interlayer insulating film may have the first height.

公开(公告)号：US09627542B2

公开(公告)日：2017-04-18

申请号：US15144662

申请日：2016-05-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoung-Ho Kwon ,  Cheol Kim ,  Ho-Young Kim ,  Se-Jung Park ,  Myeong-Cheol Kim ,  Bo-Kyeong Kang ,  Bo-Un Yoon ,  Jae-Kwang Choi ,  Si-Young Choi ,  Suk-Hoon Jeong ,  Geum-Jung Seong ,  Hee-Don Jeong ,  Yong-Joon Choi ,  Ji-Eun Han

IPC: H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/423 ,  H01L21/84 ,  H01L27/12 ,  H01L21/8238 ,  H01L29/49

CPC classification number: H01L29/7853 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/42364 ,  H01L29/4238 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785

Abstract: Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.

公开(公告)号：US20140206169A1

公开(公告)日：2014-07-24

申请号：US13834118

申请日：2013-03-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Hoon Cha ,  Jae-Jik Baek ,  Bo-Un Yoon ,  Young-Sang Youn ,  Jeong-Nam Han

IPC: H01L29/66

CPC classification number: H01L29/66628 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/76229 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method of forming a semiconductor device can include providing a plasma nitrided exposed top surface including an active region and an isolation region. The exposed top surface including the active region and the isolation region can be subjected to etching to form a deeper recess in the active region that in the isolation region and an unmerged epitaxial stress film can be grown in the deeper recess.

Abstract translation: 形成半导体器件的方法可以包括提供包括有源区和隔离区的等离子体氮化的暴露顶表面。 包括有源区和隔离区的暴露的顶表面可以进行蚀刻，以在有源区中形成更深的凹槽，在隔离区中形成较深的凹槽，并且在较深的凹槽中可以生长未熔合的外延应力膜。

公开(公告)号：US10297474B2

公开(公告)日：2019-05-21

申请号：US14183994

申请日：2014-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Jine Park ,  Bo-Un Yoon ,  Jeong-Nam Han ,  Kee-Sang Kwon ,  Doo-Sung Yun ,  Won-Sang Choi

IPC: H01L21/67

Abstract: A chemical supplier includes a chemical reservoir containing a chemical mixture at a room temperature, an inner space of the chemical reservoir being separated from surroundings, a supply line through which the chemical mixture is supplied to a process chamber from the chemical reservoir, an inline heater positioned on the supply line and heating the chemical mixture in the supply line to a process temperature, and a power source driving the chemical mixture to move the chemical mixture toward the process chamber.