公开(公告)号：US09870950B2

公开(公告)日：2018-01-16

申请号：US15371646

申请日：2016-12-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chang-Sun Hwang ,  Ja-Eung Koo ,  Jong-Hyung Park ,  Ho-Young Kim ,  Leian Bartolome ,  Bo-Un Yoon ,  Hyoung-Bin Moon

IPC: H01L21/8234 ,  H01L21/28 ,  H01L21/3105 ,  H01L29/66

CPC classification number: H01L21/823456 ,  H01L21/28008 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L28/00 ,  H01L29/66545

Abstract: A method of manufacturing a semiconductor device according to one or more exemplary embodiments of the present inventive concept includes forming a plurality of dummy gates on a substrate. Each of the dummy gates includes a gate mask disposed on an upper surface of each of the dummy gates. A spacer is disposed on at least two sides of the dummy gates. An insulating interlayer is formed on the gate mask and the spacer. A first polishing including chemical mechanical polishing is performed on portions of the gate mask and the insulating interlayer by using a slurry composite having a first mixing ratio. A second polishing including chemical mechanical polishing is formed on remaining portions of the gate mask and the insulating interlayer to expose upper surfaces of the plurality of dummy gates, by using a slurry composite having a second mixing ratio.

公开(公告)号：US11189572B2

公开(公告)日：2021-11-30

申请号：US16383816

申请日：2019-04-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung-Tae Lee ,  Seung-Hoon Choi ,  Min-Chan Gwak ,  Ja-Eung Koo ,  Sang-Hyun Park

IPC: H01L23/544 ,  H01L29/78 ,  H01L29/417 ,  H01L29/51 ,  H01L29/423

Abstract: A semiconductor device may include a gate electrode structure on a first region of a substrate including the first region and a second region, a capping structure covering an upper surface of the gate electrode structure, the capping structure including a capping pattern and a first etch stop pattern covering a lower surface and a sidewall of the capping pattern, an alignment key on the second region of the substrate, the alignment key including an insulating material, and a filling structure on the second region of the substrate, the filling structure covering a sidewall of the alignment key, and including a first filling pattern, a second filling pattern covering a lower surface and a sidewall of the first filling pattern and a second etch stop pattern covering a lower surface and a sidewall of the second filling pattern.

公开(公告)号：US10056466B2

公开(公告)日：2018-08-21

申请号：US15191555

申请日：2016-06-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-Jae Lee ,  Ja-Eung Koo ,  Ho-Young Kim ,  Yeong-Bong Park ,  Il-Su Park ,  Bo-Un Yoon ,  Il-Young Yoon ,  Youn-Su Ha

IPC: H01L29/66 ,  H01L21/321 ,  H01L21/3105 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/66545 ,  H01L21/31051 ,  H01L21/3212 ,  H01L21/823437 ,  H01L21/82345 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/517

Abstract: A method for fabricating a semiconductor device may comprise forming a first transistor having a first threshold voltage in a first region of a substrate, forming a second transistor having a second threshold voltage less than the first threshold voltage in a second region of the substrate, forming a third interlayer insulating film in the third region, and planarizing the first transistor, the second transistor and the third interlayer insulating film. The first transistor may include a first gate electrode having a first height and a first interlayer insulating film having the first height, and the second transistor may include a second gate electrode having a second height shorter than the first height and a second interlayer insulating film having the second height. The third interlayer insulating film may have the first height.

公开(公告)号：US10910266B2

公开(公告)日：2021-02-02

申请号：US16295751

申请日：2019-03-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Hoon Choi ,  Ja-Eung Koo ,  Kwan-Sik Kim ,  Dong-Chan Kim ,  Il-Young Yoon ,  Man-Geun Cho

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/48 ,  H01L23/528 ,  H01L27/30 ,  H01L27/146 ,  H01L21/321

Abstract: A method of manufacturing a semiconductor device includes forming a via including a first conductive material on an inner wall of a trench on a substrate. The method further includes forming a first insulating interlayer on the substrate. The first insulating interlayer covers the via and partially fills the trench, and the first insulating interlayer has a non-flat upper surface. The method further includes forming a polishing stop layer on the first insulating interlayer, forming a second insulating interlayer on the polishing stop layer, in which the second insulating interlayer fills a remaining portion of the trench, planarizing the second insulating interlayer until the polishing stop layer is exposed, and etching the polishing stop layer and the first and second insulating interlayers using a dry etching process until remaining portions of the polishing stop layer except for a portion of the polishing stop layer in the trench are removed.

公开(公告)号：US11361995B2

公开(公告)日：2022-06-14

申请号：US17146597

申请日：2021-01-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Hoon Choi ,  Ja-Eung Koo ,  Kwan-Sik Kim ,  Dong-Chan Kim ,  Il-Young Yoon ,  Man-Geun Cho

IPC: H01L21/768 ,  H01L21/321 ,  H01L27/146 ,  H01L23/52 ,  H01L23/522 ,  H01L23/528 ,  H01L23/48 ,  H01L27/30

Abstract: A method of manufacturing a semiconductor device includes forming a via including a first conductive material on an inner wall of a trench on a substrate. The method further includes forming a first insulating interlayer on the substrate. The first insulating interlayer covers the via and partially fills the trench, and the first insulating interlayer has a non-flat upper surface. The method further includes forming a polishing stop layer on the first insulating interlayer, forming a second insulating interlayer on the polishing stop layer, in which the second insulating interlayer fills a remaining portion of the trench, planarizing the second insulating interlayer until the polishing stop layer is exposed, and etching the polishing stop layer and the first and second insulating interlayers using a dry etching process until remaining portions of the polishing stop layer except for a portion of the polishing stop layer in the trench are removed.

公开(公告)号：US20210166976A1

公开(公告)日：2021-06-03

申请号：US17146597

申请日：2021-01-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Hoon Choi ,  Ja-Eung Koo ,  Kwan-Sik Kim ,  Dong-Chan Kim ,  Il-Young Yoon ,  Man-Geun Cho

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/48 ,  H01L27/30 ,  H01L21/321

Abstract: A method of manufacturing a semiconductor device includes forming a via including a first conductive material on an inner wall of a trench on a substrate. The method further includes forming a first insulating interlayer on the substrate. The first insulating interlayer covers the via and partially fills the trench, and the first insulating interlayer has a non-flat upper surface. The method further includes forming a polishing stop layer on the first insulating interlayer, forming a second insulating interlayer on the polishing stop layer, in which the second insulating interlayer fills a remaining portion of the trench, planarizing the second insulating interlayer until the polishing stop layer is exposed, and etching the polishing stop layer and the first and second insulating interlayers using a dry etching process until remaining portions of the polishing stop layer except for a portion of the polishing stop layer in the trench are removed.

公开(公告)号：US10032890B2

公开(公告)日：2018-07-24

申请号：US15361516

申请日：2016-11-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jun-Hwan Yim ,  Yeon-Tack Ryu ,  Joo-Cheol Han ,  Ja-Eung Koo ,  No-Ul Kim ,  Ho-Young Kim ,  Bo-Un Yoon

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51

Abstract: Disclosed is a method of manufacturing semiconductor devices. A gate trench and an insulation pattern defined by the gate trench are formed on a substrate and the protection pattern is formed on the insulation pattern. A gate dielectric layer, a work function metal layer and a sacrificial layer are sequentially formed the substrate along a surface profile of the gate trench. A sacrificial pattern is formed by a CMP while not exposing the insulation pattern. A residual sacrificial pattern is formed at a lower portion of the gate trench and the gate dielectric layer and the work function metal layer is etched into a gate dielectric pattern and a work function metal pattern using the residual sacrificial pattern as an etch stop layer.