公开(公告)号：US20230168838A1

公开(公告)日：2023-06-01

申请号：US17827841

申请日：2022-05-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNGSUK MOON ,  JAEGEUN PARK ,  JONGIN LEE ,  SANGMUK HWANG

IPC: G06F3/06

CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0679

Abstract: A memory controller includes a buffer memory including memory banks, one or more host access units configured to perform an access to the buffer memory for a host, one or more memory access units configured to perform an access to the buffer memory for a memory device, and a processor configured to control an operation of the memory controller. The processor divides the memory banks into an external memory bank group for an external operation related to the host, and an internal memory bank group for an internal operation within a memory system. The host access units access the external memory bank group. The memory access units access the external memory bank group to perform the external operation, and access the internal memory bank group to perform the internal operation.

公开(公告)号：US20210191884A1

公开(公告)日：2021-06-24

申请号：US16983471

申请日：2020-08-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SANGMUK HWANG ,  JAEGEUN PARK ,  HOJUN SHIM ,  BYUNGCHUL YOO

IPC: G06F13/16 ,  G06F13/28

Abstract: A method of operating a storage controller that communicates with a host including a submission queue and a completion queue is provided. The operating method includes receiving a submission queue doorbell from the host, fetching a first command including a latency from the submission queue of the host in response to the received submission queue doorbell, processing the fetched first command, and writing a first completion, which indicates that the first command is completely processed, into the completion queue of the host at a timing based on the latency.

公开(公告)号：US20200183619A1

公开(公告)日：2020-06-11

申请号：US16789526

申请日：2020-02-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JINWOO KIM ,  JAEGEUN PARK ,  YOUNGJIN CHO

IPC: G06F3/06 ,  G06F12/0868 ,  G06F11/10 ,  G06F13/28 ,  G06F12/0831

Abstract: A read method executed by a computing system includes a processor, at least one nonvolatile memory, and at least one cache memory performing a cache function of the at least one nonvolatile memory. The method includes receiving a read request regarding a critical word from the processor. A determination is made whether a cache miss is generated, through a tag determination operation corresponding to the read request. Page data corresponding to the read request is received from the at least one nonvolatile memory in a wraparound scheme when a result of the tag determination operation indicates that the cache miss is generated. The critical word is output to the processor when the critical word of the page data is received.

公开(公告)号：US20170062040A1

公开(公告)日：2017-03-02

申请号：US15249333

申请日：2016-08-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： YOUNGJIN CHO ,  JAEGEUN PARK ,  Youngkwang YOO

IPC: G11C11/4074 ,  G11C7/10 ,  G06F1/32 ,  G11C11/406

CPC classification number: G11C11/4074 ,  G06F1/3287 ,  G11C11/40615 ,  G11C11/40626 ,  G11C2211/4067

Abstract: A dynamic random access memory (DRAM) device includes a memory cell array including a plurality of memory cells, a refresh controller configured to perform a plurality of refresh operations on the plurality of memory cells in response to a plurality of refresh commands from an external device, and a refresh counter configured to count a number of the refresh commands for a fixed period of time and compare the counted number with a threshold. The refresh counter is configured to generate a power failure signal to cause the DRAM device to enter a power failure mode in response to the comparison of the counted number with the threshold. The refresh controller is configured to perform a refresh operation on the plurality of memory cells without control of the external device in the power failure mode.

Abstract translation: 动态随机存取存储器（DRAM）装置包括包括多个存储器单元的存储单元阵列，刷新控制器，被配置为响应于来自外部设备的多个刷新命令对所述多个存储器单元执行多个刷新操作 以及刷新计数器，被配置为在固定时间段内对多个刷新命令进行计数，并将计数的数量与阈值进行比较。 刷新计数器被配置为响应于计数的数量与阈值的比较而产生电源故障信号以使DRAM设备进入电源故障模式。 刷新控制器被配置为在电源故障模式下不对外部设备进行控制，对多个存储单元执行刷新操作。

公开(公告)号：US20160358657A1

公开(公告)日：2016-12-08

申请号：US15083834

申请日：2016-03-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JINWOO KIM ,  SEONG YEON KIM ,  JAEGEUN PARK ,  HYO-DEOK SHIN ,  YOUNGGEUN LEE ,  YOUNGJIN CHO

IPC: G11C16/10

CPC classification number: G11C16/10 ,  G11C7/1063

Abstract: A nonvolatile memory system includes first and second nonvolatile memory devices and a memory controller configured to control the first and second nonvolatile memory devices through one channel. During a program operation, the memory controller transmits first signals, for setting first page data up in the first nonvolatile memory device, to the first nonvolatile memory device through the channel. While the first nonvolatile memory device sets up the first page data in response to the first signals, the memory controller transmits second signals, for setting second page data up in the second nonvolatile memory device, to the second nonvolatile memory device.

Abstract translation: 非易失性存储器系统包括第一和第二非易失性存储器件以及被配置为通过一个通道来控制第一和第二非易失性存储器件的存储器控​​制器。 在程序操作期间，存储器控制器通过通道向第一非易失性存储器件发送用于将第一非易失性存储器件中的第一页数据向上设置的第一信号。 当第一非易失性存储装置响应于第一信号设置第一页数据时，存储器控制器将用于将第二页数据向上设置在第二非易失存储装置中的第二信号发送到第二非易失存储装置。