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公开(公告)号:US20160327975A1
公开(公告)日:2016-11-10
申请号:US15057380
申请日:2016-03-01
Applicant: Samsung Electronics Co., Ltd.
Inventor: JE KOOK KIM , Chan Woo Park , Min Shik Seok
CPC classification number: G06F1/12 , G06F1/305 , H03K5/15013
Abstract: An integrated circuit configured to detect a variation in a supply voltage using a phase of an input clock signal dependent on the variation in the supply voltage may include a clock delay circuit configured to delay the input clock signal output from a clock generator using each of different delay cell chains and generate a first delay clock signal and a second delay clock signal; and a phase controller configured to control a first phase so that a difference between the first phase and a second phase is 180 degrees, the first phase being a phase of the first delay clock signal, the second phase being a phase of the second delay clock signal.
Abstract translation: 被配置为使用取决于电源电压的变化的输入时钟信号的相位来检测电源电压的变化的集成电路可以包括时钟延迟电路,其被配置为使用每个不同的时钟发生器来延迟从时钟发生器输出的输入时钟信号 延迟单元链并产生第一延迟时钟信号和第二延迟时钟信号; 以及相位控制器,被配置为控制第一相位,使得第一相位和第二相位之间的差为180度,第一相位为第一延迟时钟信号的相位,第二相位为第二延迟时钟的相位 信号。
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公开(公告)号:US20190220075A1
公开(公告)日:2019-07-18
申请号:US16357408
申请日:2019-03-19
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: JE KOOK KIM
IPC: G06F1/26 , G06F1/3296 , G06F13/42 , G06F1/10
CPC classification number: G06F1/266 , G06F1/10 , G06F1/324 , G06F1/3253 , G06F1/3296 , G06F13/385 , G06F13/4282 , G06F2213/0042 , Y02D10/14 , Y02D10/151
Abstract: A USB power-delivery device includes a clock signal generator which stops generation of a clock signal for a dual-role port (DRP) while the USB power-delivery device operates in a low power mode until an attach event occurs, and starts the generation of the clock signal for the DRP after the attach event occurs.
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公开(公告)号:US20170220090A1
公开(公告)日:2017-08-03
申请号:US15277515
申请日:2016-09-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: JE KOOK KIM
CPC classification number: G06F1/266 , G06F1/324 , G06F1/3253 , G06F13/385 , G06F13/4282 , Y02D10/14 , Y02D10/151
Abstract: A USB power-delivery device includes a clock signal generator which stops generation of a clock signal for a dual-role port (DRP) while the USB power-delivery device operates in a low power mode until an attach event occurs, and starts the generation of the clock signal for the DRP after the attach event occurs.
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