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    PHASE LOCKED LOOP AND OPERATING METHOD OF PHASE LOCKED LOOP
    1.
    发明申请
    PHASE LOCKED LOOP AND OPERATING METHOD OF PHASE LOCKED LOOP 有权

    公开(公告)号：US20220360270A1

    公开(公告)日：2022-11-10

    申请号：US17734693

    申请日：2022-05-02

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： SANGDON JUNG ,  GYUSIK KIM ,  SEUNGJIN KIM ,  SEUNGHYUN OH ,  JIHWAN KIM

    IPC: H03L7/10 ,  H03L7/089 ,  H03L7/099

    Abstract: A phase locked loop includes a phase detector outputting a first signal corresponding to a phase difference of a reference frequency signal and a division frequency signal, a charge pump amplifying a first signal to output a second signal, a loop filter filtering the second signal to output a third signal, a voltage-to-current converter receiving the third signal and outputting a fourth signal, a digital-to-analog converter outputting a fifth signal based on the fourth signal and a digital compensation signal, an oscillator outputting an output frequency signal having a frequency corresponding to the fifth signal, a divider dividing the frequency of the output frequency signal to output the division frequency signal and a compensation frequency signal, and an automatic frequency calibrator compensating for the voltage-to-current converter based on a difference between a frequency of the compensation frequency signal and a frequency of a reference frequency signal.

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