公开(公告)号：US20190081174A1

公开(公告)日：2019-03-14

申请号：US16044584

申请日：2018-07-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUNG-GUN YOU ,  Chang-Hee Kim ,  Sung-II Park ,  Dong-Hun Lee

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L23/532 ,  H01L21/308 ,  H01L21/8238

Abstract: A vFET includes a first impurity region doped with first impurities at an upper portion of the substrate. A first diffusion control pattern is formed on the first impurity region. The first diffusion control pattern is configured to control the diffusion of the first impurities. A channel extends in a vertical direction substantially orthogonal to an upper surface of the substrate. A second impurity region is doped with second impurities on the channel. A second diffusion control pattern is between the channel and the second impurity region. The second diffusion control pattern is configured to control the diffusion of the second impurities. A gate structure is adjacent to the channel.

公开(公告)号：US20170221771A1

公开(公告)日：2017-08-03

申请号：US15489782

申请日：2017-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： JUNG-GUN YOU ,  EUNG-GWAN KIM ,  JEONG-YUN LEE

IPC: H01L21/8238 ,  H01L21/02 ,  H01L27/092 ,  H01L29/78 ,  H01L29/161 ,  H01L29/16 ,  H01L29/165 ,  H01L29/08 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L21/823828 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

Abstract: Spaced apart first and second fins are formed on a substrate. An isolation layer is formed on the substrate between the first and second fins. A gate electrode is formed on the isolation layer and crossing the first and second fins. Source/drain regions are formed on the first and second fins adjacent the gate electrode. After forming the source/drain regions, a portion of the gate electrode between the first and second fins is removed to expose the isolation layer. The source/drain regions may be formed by epitaxial growth.

公开(公告)号：US20200185382A1

公开(公告)日：2020-06-11

申请号：US16794029

申请日：2020-02-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： JUNG-GUN YOU ,  Se-wan Park ,  Baik-Min Sung ,  Bo-Cheol Jeong

IPC: H01L27/088 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66

Abstract: Semiconductor devices are provided including a first fin-shaped pattern having first and second sidewalls facing one another and a field insulating film contacting at least a portion of the first fin-shaped pattern. The first fin-shaped pattern includes a lower portion of the first fin-shaped pattern contacting the field insulating film; an upper portion of the first fin-shaped pattern not contacting the field insulating film; a first boundary between the lower portion of the first fin-shaped pattern and the upper portion of the first fin-shaped pattern; and a first fin center line perpendicular to the first boundary and meeting the top of the upper portion of the first fin-shaped pattern. The first sidewall of the upper portion of the first fin-shaped pattern and the second sidewall of the upper portion of the first fin-shaped pattern are asymmetric with respect to the first fin center line.

公开(公告)号：US20160020150A1

公开(公告)日：2016-01-21

申请号：US14803893

申请日：2015-07-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： JUNG-GUN YOU ,  EUNG-GWAN KIM ,  JEONG-YUN LEE

IPC: H01L21/8238 ,  H01L21/3213 ,  H01L29/165 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823828 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

Abstract: Spaced apart first and second fins are formed on a substrate. An isolation layer is formed on the substrate between the first and second fins. A gate electrode is formed on the isolation layer and crossing the first and second fins. Source/drain regions are formed on the first and second fins adjacent the gate electrode. After forming the source/drain regions, a portion of the gate electrode between the first and second fins is removed to expose the isolation layer. The source/drain regions may be formed by epitaxial growth.

Abstract translation: 隔开的第一和第二散热片形成在基板上。 在第一和第二鳍片之间的衬底上形成隔离层。 栅电极形成在隔离层上并与第一和第二鳍交叉。 源极/漏极区域形成在与栅电极相邻的第一和第二鳍片上。 在形成源极/漏极区域之后，去除第一和第二鳍片之间的栅电极的一部分以暴露隔离层。 源/漏区可以通过外延生长形成。

公开(公告)号：US20200220012A1

公开(公告)日：2020-07-09

申请号：US16816908

申请日：2020-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUNG-GUN YOU ,  Chang-Hee KIM ,  Sung-II PARK ,  Dong-Hun LEE

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L21/8238 ,  H01L21/308 ,  H01L23/532 ,  H01L29/10 ,  H01L29/06

Abstract: A vFET includes a first impurity region doped with first impurities at an upper portion of the substrate. A first diffusion control pattern is formed on the first impurity region. The first diffusion control pattern is configured to control the diffusion of the first impurities. A channel extends in a vertical direction substantially orthogonal to an upper surface of the substrate. A second impurity region is doped with second impurities on the channel. A second diffusion control pattern is between the channel and the second impurity region. The second diffusion control pattern is configured to control the diffusion of the second impurities. A gate structure is adjacent to the channel.

公开(公告)号：US20190131300A1

公开(公告)日：2019-05-02

申请号：US16233301

申请日：2018-12-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： JUNG-GUN YOU ,  Se-wan Park ,  Baik-Min Sung ,  Bo-Cheol Jeong

IPC: H01L27/088 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7853 ,  H01L29/7854

Abstract: Semiconductor devices are provided including a first fin-shaped pattern having first and second sidewalls facing one another and a field insulating film contacting at least a portion of the first fin-shaped pattern. The first fin-shaped pattern includes a lower portion of the first fin-shaped pattern contacting the field insulating film; an upper portion of the first fin-shaped pattern not contacting the field insulating film; a first boundary between the lower portion of the first fin-shaped pattern and the upper portion of the first fin-shaped pattern; and a first fin center line perpendicular to the first boundary and meeting the top of the upper portion of the first fin-shaped pattern. The first sidewall of the upper portion of the first fin-shaped pattern and the second sidewall of the upper portion of the first fin-shaped pattern are asymmetric with respect to the first fin center line.