公开(公告)号：US20180374869A1

公开(公告)日：2018-12-27

申请号：US15993756

申请日：2018-05-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwang-soo KIM ,  Yong-seok KIM ,  Tae-hun KIM ,  Min-kyung BAE ,  Jae-hoon JANG ,  Kohji KANAMORI

IPC: H01L27/11582 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L27/11582 ,  H01L27/11565 ,  H01L29/0847 ,  H01L29/7827

Abstract: A semiconductor device includes a plurality of channel structures on a substrate, each channel structure extending in a first direction perpendicular to the substrate, and having a gate insulating layer and a channel layer, a common source extension region including a first semiconductor layer having an n-type conductivity between the substrate and the channel structures, a plurality of gate electrodes on the common source extension region and spaced apart from each other on a sidewall of each of the channel structures in the first direction, and a common source region on the substrate in contact with the common source extension region and including a second semiconductor layer having an n-type conductivity, wherein the gate insulating layer of each of the channel structures extends to cover an upper surface and at least a portion of a bottom surface of the common source extension region.

公开(公告)号：US20190355744A1

公开(公告)日：2019-11-21

申请号：US16526139

申请日：2019-07-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwang-soo KIM ,  Yong-seok KIM ,  Tae-hun KIM ,  Min-kyung BAE ,  Jae-hoon JANG ,  Kohji KANAMORI

IPC: H01L27/11582 ,  H01L29/08 ,  H01L29/78

Abstract: A semiconductor device includes a plurality of channel structures on a substrate, each channel structure extending in a first direction perpendicular to the substrate, and having a gate insulating layer and a channel layer, a common source extension region including a first semiconductor layer having an n-type conductivity between the substrate and the channel structures, a plurality of gate electrodes on the common source extension region and spaced apart from each other on a sidewall of each of the channel structures in the first direction, and a common source region on the substrate in contact with the common source extension region and including a second semiconductor layer having an n-type conductivity, wherein the gate insulating layer of each of the channel structures extends to cover an upper surface and at least a portion of a bottom surface of the common source extension region.

公开(公告)号：US20180226423A1

公开(公告)日：2018-08-09

申请号：US15946432

申请日：2018-04-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shin-hwan KANG ,  Young-hwan SON ,  Dong-seog EUN ,  Chang-sup LEE ,  Jae-hoon JANG

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157

CPC classification number: H01L27/11556 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582

Abstract: In one embodiment, the semiconductor device includes a stack of alternating interlayer insulating layers and conductive layers on a substrate. Each of the conductive layers extends in a first direction less than a previous one of the conductive layers to define a landing portion of the previous one of the conductive layers. An insulating plug is in one of the conductive layers under one of the landing portions, and a contact plug extends from an upper surface of the one of the landing portions.

公开(公告)号：US20150011064A1

公开(公告)日：2015-01-08

申请号：US14495397

申请日：2014-09-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-min HWANG ,  Han-soo KIM ,  Won-seok CHO ,  Jae-hoon JANG

IPC: H01L27/115 ,  H01L21/768 ,  H01L21/306 ,  H01L21/285 ,  H01L21/265 ,  H01L29/66

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  H01L21/265 ,  H01L21/28518 ,  H01L21/30604 ,  H01L21/768 ,  H01L27/11578 ,  H01L29/6656

Abstract: Provided is a vertical non-volatile memory device having a metal source line. The vertical non-volatile memory device includes cell string units that are formed on first portions of a semiconductor substrate and are vertically arranged with respect to a surface of the semiconductor substrate, impurity regions formed on second portions of the semiconductor substrate between the cell string units, conductive lines formed on the impurity regions, and spacers that are formed on the sidewalls of the cell string units and insulate the conductive lines from the cells string units.

Abstract translation: 提供了具有金属源线的垂直非易失性存储器件。 垂直非易失性存储器件包括形成在半导体衬底的第一部分上且相对于半导体衬底的表面垂直布置的单元串单元，形成在半导体衬底的第二部分之间的细胞串单元 在杂质区上形成的导电线，以及形成在电池串单元的侧壁上的间隔物，并使导电线与电池串单元绝缘。