Apparatus and method using programmable reliability aging timer

    公开(公告)号:US10145891B2

    公开(公告)日:2018-12-04

    申请号:US14856837

    申请日:2015-09-17

    Abstract: An apparatus and a method which use a programmable reliability aging timer are provided. The apparatus includes a performance circuit configured to perform a function of an integrated circuit (IC), a memory unit configured to store a lifetime of the IC, a controller configured to set an aging target condition according to the lifetime stored in the memory unit, and a reliability aging timer (RAT) configured to apply stress to a test pattern according to the aging target condition and sense a result of the stress to determine the degradation of the IC. The RAT refreshes an operation of the performance circuit if it is determined that the IC degraded before the lifetime of the IC.

    FREQUENCY DIVIDER AND A TRANSCEIVER INCLUDING THE SAME

    公开(公告)号:US20190165790A1

    公开(公告)日:2019-05-30

    申请号:US16202172

    申请日:2018-11-28

    Abstract: A frequency divider may include: a core circuit including a first flip-flop loop and a second flip-flop loop, wherein each of the first flip-flop loop and the second flip-flop loop divides a frequency of a clock signal received via a control terminal of a flip-flop, wherein the core circuit is configured to: output a frequency-divided signal, based on a first signal output by the first flip-flop loop and a second signal output by the second flip-flop loop, the first and second signals having same frequency-division ratios and different phases, and feed back the frequency-divided signal via an input terminal of each of the first and second flip-flop loops; a duty correction circuit that receives the frequency-divided signal and outputs a differential output signal that is generated by correcting a duty ratio of the frequency-divided signal; and an output circuit that outputs a first output signal, which is a signal amplified from the differential output signal, and a second output signal that is a quadrature signal of the first output signal.

    Frequency divider and a transceiver including the same

    公开(公告)号:US10547315B2

    公开(公告)日:2020-01-28

    申请号:US16202172

    申请日:2018-11-28

    Abstract: A frequency divider may include: a core circuit including a first flip-flop loop and a second flip-flop loop, wherein each of the first flip-flop loop and the second flip-flop loop divides a frequency of a clock signal received via a control terminal of a flip-flop, wherein the core circuit is configured to: output a frequency-divided signal, based on a first signal output by the first flip-flop loop and a second signal output by the second flip-flop loop, the first and second signals having same frequency-division ratios and different phases, and feed back the frequency-divided signal via an input terminal of each of the first and second flip-flop loops; a duty correction circuit that receives the frequency-divided signal and outputs a differential output signal that is generated by correcting a duty ratio of the frequency-divided signal; and an output circuit that outputs a first output signal, which is a signal amplified from the differential output signal, and a second output signal that is a quadrature signal of the first output signal.

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