公开(公告)号：US20150043267A1

公开(公告)日：2015-02-12

申请号：US14257391

申请日：2014-04-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung-chang Ryoo ,  Hongsik Jeong ,  Daehwan Kang ,  JaeHee Oh ,  Jihyung Yu

IPC: G11C13/00 ,  H01L27/24

CPC classification number: G11C13/0004 ,  G11C13/0007 ,  G11C14/00 ,  G11C2213/32 ,  G11C2213/72 ,  H01L27/224 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/165

Abstract: A variable resistance memory system includes a variable resistance memory device including a memory cell array including first and second areas; and a memory controller configured to control the variable resistance memory device. The first area includes first variable resistance memory cells including a first variable resistance material layer and the second area includes second variable resistance memory cells including a second variable resistance material layer having a metallic doping concentration higher than a metallic doping concentration of the first variable resistance material layer. The first variable resistance memory cells are used as storage and the second variable resistance memory cells are used as a buffer memory.

Abstract translation: 可变电阻存储器系统包括可变电阻存储器件，其包括包括第一和第二区域的存储单元阵列; 以及被配置为控制可变电阻存储器件的存储器控​​制器。 第一区域包括包括第一可变电阻材料层的第一可变电阻存储单元，并且第二区域包括第二可变电阻存储单元，其包括金属掺杂浓度高于第一可变电阻材料的金属掺杂浓度的第二可变电阻材料层 层。 第一可变电阻存储单元用作存储器，第二可变电阻存储单元用作缓冲存储器。

公开(公告)号：US09710747B2

公开(公告)日：2017-07-18

申请号：US14328359

申请日：2014-07-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daehwan Kang ,  Kyung-chang Ryoo ,  Hyun Goo Jun ,  Hongsik Jeong ,  JaeHee Oh

IPC: G06N3/063 ,  G06N3/04

CPC classification number: G06N3/063 ,  G06N3/049

Abstract: A method of generating neuron spiking pulses in a neuromorphic system is provided which includes floating one or more selected bit lines connected to target cells, having a first state, from among a plurality of memory cells arranged at intersections of a plurality of word lines and a plurality of bit lines; and stepwisely increasing voltages applied to unselected word lines connected to unselected cells, having a second state, from among memory cells connected to the one or more selected bit lines other than the target cells having the first state.

公开(公告)号：US09230642B2

公开(公告)日：2016-01-05

申请号：US14257391

申请日：2014-04-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung-chang Ryoo ,  Hongsik Jeong ,  Daehwan Kang ,  JaeHee Oh ,  Jihyung Yu

IPC: G11C11/00 ,  G11C13/00 ,  G11C14/00 ,  H01L45/00 ,  H01L27/22 ,  H01L27/24

CPC classification number: G11C13/0004 ,  G11C13/0007 ,  G11C14/00 ,  G11C2213/32 ,  G11C2213/72 ,  H01L27/224 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/165

Abstract: A variable resistance memory system includes a variable resistance memory device including a memory cell array including first and second areas; and a memory controller configured to control the variable resistance memory device. The first area includes first variable resistance memory cells including a first variable resistance material layer and the second area includes second variable resistance memory cells including a second variable resistance material layer having a metallic doping concentration higher than a metallic doping concentration of the first variable resistance material layer. The first variable resistance memory cells are used as storage and the second variable resistance memory cells are used as a buffer memory.

Abstract translation: 可变电阻存储器系统包括可变电阻存储器件，其包括包括第一和第二区域的存储单元阵列; 以及被配置为控制可变电阻存储器件的存储器控​​制器。 第一区域包括包括第一可变电阻材料层的第一可变电阻存储单元，并且第二区域包括第二可变电阻存储单元，其包括金属掺杂浓度高于第一可变电阻材料的金属掺杂浓度的第二可变电阻材料层 层。 第一可变电阻存储单元用作存储器，第二可变电阻存储单元用作缓冲存储器。