公开(公告)号：US20240323570A1

公开(公告)日：2024-09-26

申请号：US18610971

申请日：2024-03-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myeongjin OH ,  Mooyoung KIM ,  Jaejung PARK ,  Haneul JUNG

IPC: H04N25/76 ,  H03K4/06 ,  H04N25/77 ,  H04N25/78

CPC classification number: H04N25/7795 ,  H03K4/06 ,  H04N25/78 ,  H04N25/77

Abstract: A ramp signal generator includes a clock divider configured to generate a plurality of ramp clocks having different clocks, an output bit selector configured to select an output bit for reading out a pixel signal based on an analog gain of a ramp signal, a ramp clock controller configured to set a clock corresponding to the output bit, from among the plurality of ramp clocks, as a ramp clock, and a ramp offset controller configured to set an offset value corresponding to the output bit, from among a plurality of offset values, as a ramp offset value.

公开(公告)号：US20240179434A1

公开(公告)日：2024-05-30

申请号：US18467318

申请日：2023-09-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjae HAN ,  Jaejung PARK ,  Seunghyun LIM ,  Haneul JUNG

IPC: H04N25/75 ,  H04N25/616 ,  H04N25/65

CPC classification number: H04N25/75 ,  H04N25/616 ,  H04N25/65

Abstract: A ramp signal generator may include a current cell unit including a plurality of current sources configured to generate current signals, and a resistance unit connected to an output terminal of the current cell unit. The resistance unit may include a load resistor and an offset resistor connected in series with the load resistor and having a resistance based on analog gains.

公开(公告)号：US20230156372A1

公开(公告)日：2023-05-18

申请号：US17986966

申请日：2022-11-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myeongjin OH ,  Jaejung PARK ,  Sukho SHIN ,  Haneul JUNG

IPC: H04N5/3745 ,  H03M1/76 ,  H04N5/378

CPC classification number: H04N5/37455 ,  H03M1/76 ,  H04N5/378

Abstract: A digital-to-analog converter includes a first channel configured to output a first ramp voltage through an output node, and a first bias circuit configured to apply a bias voltage to the first channel. The first channel comprises a plurality of current cells connected to the first bias circuit, a plurality of selection circuits and a plurality of switches, and a first resistor connected to the output node. Each of the plurality of selection circuits of the first channel comprises a first selection circuit configured to connect a current of one of the plurality of current cells to the first resistor in accordance with a first digital input signal, and a second selection circuit configured to connect the current of the current cell to one of the plurality of switches corresponding to the current cell in accordance with a second digital input signal complementary to the first digital input signal.

公开(公告)号：US20230053956A1

公开(公告)日：2023-02-23

申请号：US17718450

申请日：2022-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myeongjin OH ,  Jaejung PARK ,  Hyosang KIM ,  Sukho SHIN ,  Haneul JUNG

IPC: H04N5/378 ,  H04N5/3745

Abstract: In an example embodiment, a ramp generator includes a ramp circuit that receives a first ramp enable signal from a control circuit during a first ramp period, the first ramp period including a first reset period and a first sensing period, and the ramp circuit being configured to output a first ramp signal to a correlated double sampling circuit; an emphasis circuit that increases a voltage level of the first ramp signal during the first reset period, based on a first enable signal received from the control circuit; and a pre-emphasis circuit that further increases the voltage level of the first ramp signal during a first pre-emphasis period in the first reset period, based on a second enable signal received from the control circuit.

公开(公告)号：US20210201835A1

公开(公告)日：2021-07-01

申请号：US16940535

申请日：2020-07-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyuik CHO ,  Jaejung PARK

IPC: G09G3/34 ,  G06T7/30 ,  G06T3/40

Abstract: A driver circuit of an image sensor is provided. The driver circuit includes a row decoder to decode an address of a target row of a pixel array and generate an operation directing signal corresponding to the target row; a digital logic circuit including: a target row logic circuit to generate a pixel control signal based on the operation directing signal; a power switch configured to connect a power supply voltage to the target row logic circuit during a first time and isolate the power supply voltage from the target row logic circuit during a second time, based on the operation directing signal; and an output circuit configured to output a default signal during the second time; and a row driver configured to drive the target row based on the pixel control signal during the first time and drive the target row based on the default signal during the second time.