公开(公告)号：US20230154886A1

公开(公告)日：2023-05-18

申请号：US18099092

申请日：2023-01-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyungu KANG ,  Jaekyu SUNG

IPC: H01L23/00 ,  H01L25/18 ,  H01L23/498

CPC classification number: H01L24/73 ,  H01L25/18 ,  H01L24/32 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L23/49816 ,  H01L2924/182 ,  H01L2924/1435 ,  H01L2924/1431 ,  H01L2224/32225 ,  H01L2224/32145 ,  H01L2224/06102 ,  H01L2224/48148 ,  H01L2224/48158 ,  H01L2224/49112 ,  H01L2224/49107 ,  H01L2224/49109 ,  H01L2224/73265

Abstract: A semiconductor package may include a semiconductor chip on a package substrate. The semiconductor package may include a plurality of conductive connections connecting the semiconductor chip to the package substrate may be disposed, a plurality of towers which are apart from one another and each include a plurality of memory chips may be disposed, wherein a lowermost memory chip of each of the plurality of towers overlaps the semiconductor chip from a top-down view. The semiconductor package further includes a plurality of adhesive layers be attached between the lowermost memory chip of each of the plurality of towers and the semiconductor chip.

公开(公告)号：US20240079380A1

公开(公告)日：2024-03-07

申请号：US18334062

申请日：2023-06-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonghyun BAEK ,  Jaekyu SUNG ,  Dongok KWAK ,  Taeyoung LEE

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L2224/32145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562

Abstract: A stacked semiconductor package may include a package base substrate, a first chip stack including a first semiconductor chips stacked sequentially on the package base substrate, a second chip stack including second semiconductor chips stacked sequentially on the first chip stack, and bonding wires electrically connecting the first semiconductor chips and the second semiconductor chips to the package base substrate. Each of the first semiconductor chips may be shifted by a first interval in a first horizontal direction to have a step shape. Each of the second semiconductor chips may be shifted by the first interval in a second horizontal direction, opposite to the first horizontal direction, to have a step shape. A lowermost second semiconductor chip may be shifted from an uppermost first semiconductor chip by a second interval in the second direction. The second interval may be greater than the first interval.

公开(公告)号：US20250167175A1

公开(公告)日：2025-05-22

申请号：US19027183

申请日：2025-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minkyeong PARK ,  Do-Hyun KIM ,  Jaekyu SUNG

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498

Abstract: A semiconductor package including a package substrate including first and second bonding pads, third bonding pads spaced apart from the first bonding pads, and fourth bonding pads spaced apart from the second bonding pads; a first chip stack including first chips stacked on the package substrate, each first chip including first signal pads and first power/ground pads alternately arranged; a second chip stack including second chips stacked on the first chip stack, each second chip including second signal pads and second power/ground pads alternately arranged; first lower wires that connect the first signal pads to the first bonding pads; second lower wires that connect the first power/ground pads to the second bonding pads; first upper wires that connect the second signal pads of the second chips to the third bonding pads; and second upper wires that connect the second power/ground pads of the second chips to the fourth bonding pads.

公开(公告)号：US20230005884A1

公开(公告)日：2023-01-05

申请号：US17665810

申请日：2022-02-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minkyeong PARK ,  Do-Hyun KIM ,  Jaekyu SUNG

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/00

Abstract: A semiconductor package including a package substrate including first and second bonding pads, third bonding pads spaced apart from the first bonding pads, and fourth bonding pads spaced apart from the second bonding pads; a first chip stack including first chips stacked on the package substrate, each first chip including first signal pads and first power/ground pads alternately arranged; a second chip stack including second chips stacked on the first chip stack, each second chip including second signal pads and second power/ground pads alternately arranged; first lower wires that connect the first signal pads to the first bonding pads; second lower wires that connect the first power/ground pads to the second bonding pads; first upper wires that connect the second signal pads of the second chips to the third bonding pads; and second upper wires that connect the second power/ground pads of the second chips to the fourth bonding pads.

公开(公告)号：US20240179925A1

公开(公告)日：2024-05-30

申请号：US18453611

申请日：2023-08-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaekyu SUNG ,  Joonghyun BAEK ,  Cheolwoo LEE

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/18

CPC classification number: H10B80/00 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L25/18 ,  H01L23/3128 ,  H01L2224/06135 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/4903 ,  H01L2224/49175

Abstract: A semiconductor package may include a substrate; at least one controller chip on the substrate; at least one chip structure on the substrate, the at least one chip structure including a buffer chip, an upper chip stack on the buffer chip, and a lower chip stack below the buffer chip; an upper wire electrically connecting the upper chip stack, the buffer chip, and the at least one controller chip; a lower wire electrically connecting the lower chip stack and the at least one controller chip; a connection wire electrically connecting the at least one controller chip to the substrate; and connection bumps below the substrate, the connection bumps being electrically connected to the at least one controller chip and the at least one chip structure.

公开(公告)号：US20220130793A1

公开(公告)日：2022-04-28

申请号：US17223614

申请日：2021-04-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyungu KANG ,  Jaekyu SUNG

IPC: H01L23/00 ,  H01L23/498 ,  H01L25/18

Abstract: A semiconductor package may include a semiconductor chip on a package substrate. The semiconductor package may include a plurality of conductive connections connecting the semiconductor chip to the package substrate may be disposed, a plurality of towers which are apart from one another and each include a plurality of memory chips may be disposed, wherein a lowermost memory chip of each of the plurality of towers overlaps the semiconductor chip from a top-down view. The semiconductor package further includes a plurality of adhesive layers be attached between the lowermost memory chip of each of the plurality of towers and the semiconductor chip.