公开(公告)号：US20230138048A1

公开(公告)日：2023-05-04

申请号：US18145186

申请日：2022-12-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngcheon Kwon ,  Jaesan Kim ,  Jemin Ryu ,  Jaeyoun Youn ,  Haesuk Lee

IPC: G06F3/06 ,  G11C7/10 ,  G11C7/22 ,  H01L25/18

Abstract: A memory device according to an aspect may include a memory cell array including a first bank region and a second bank region each including a plurality of banks; an operation logic including one or more first processing elements (PEs) corresponding to the first bank region and one or more second PEs corresponding to the second bank region; a control logic configured to control modes of the first bank region and the second bank region based on externally sourced setting information; first and second mode signal generators configured to control enabling the first PEs, wherein the first mode signal generator is configured to output the first mode signal to enable the first PEs and the second mode signal generator is configured to output the second mode signal to disable the second PEs responsive to the first bank region being set to an operation mode and the second bank region being set to a normal mode.

公开(公告)号：US12001699B2

公开(公告)日：2024-06-04

申请号：US18145186

申请日：2022-12-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngcheon Kwon ,  Jaesan Kim ,  Jemin Ryu ,  Jaeyoun Youn ,  Haesuk Lee

IPC: G06F3/06 ,  G11C7/10 ,  G11C7/22 ,  H01L25/18

CPC classification number: G06F3/0634 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G11C7/1069 ,  G11C7/222 ,  H01L25/18

Abstract: A memory device according to an aspect may include a memory cell array including a first bank region and a second bank region each including a plurality of banks; an operation logic including one or more first processing elements (PEs) corresponding to the first bank region and one or more second PEs corresponding to the second bank region; a control logic configured to control modes of the first bank region and the second bank region based on externally sourced setting information; first and second mode signal generators configured to control enabling the first PEs, wherein the first mode signal generator is configured to output the first mode signal to enable the first PEs and the second mode signal generator is configured to output the second mode signal to disable the second PEs responsive to the first bank region being set to an operation mode and the second bank region being set to a normal mode.

公开(公告)号：US20220130841A1

公开(公告)日：2022-04-28

申请号：US17496498

申请日：2021-10-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaesan Kim ,  Seunghan Woo ,  Haesuk Lee ,  Youngcheon Kwon ,  Reum Oh

IPC: H01L27/108 ,  H01L23/48 ,  H01L23/528 ,  H01L29/8605 ,  H01L29/94

Abstract: A semiconductor device includes a semiconductor structure including a semiconductor substrate having an active zone with a channel; a through silicon via (TSV) structure including a power TSV configured to transmit power and a signal TSV configured to transmit a signal; and a keep-out zone located a predetermined distance away from the TSV structure and bounded by the active zone. The TSV structure penetrates the semiconductor substrate. The keep-out zone includes a first element area a first distance away from the power TSV, and a second element area a second distance away from the signal TSV.

公开(公告)号：US20220075541A1

公开(公告)日：2022-03-10

申请号：US17335307

申请日：2021-06-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngcheon Kwon ,  Jaesan Kim ,  Jemin Ryu ,  Jaeyoun Youn ,  Haesuk Lee

IPC: G06F3/06 ,  H01L25/18 ,  G11C7/10 ,  G11C7/22

Abstract: A memory device according to an aspect may include a memory cell array including a first bank region and a second bank region each including a plurality of banks; an operation logic including one or more first processing elements (PEs) corresponding to the first bank region and one or more second PEs corresponding to the second bank region; a control logic configured to control modes of the first bank region and the second bank region based on externally sourced setting information; first and second mode signal generators configured to control enabling the first PEs, wherein the first mode signal generator is configured to output the first mode signal to enable the first PEs and the second mode signal generator is configured to output the second mode signal to disable the second PEs responsive to the first bank region being set to an operation mode and the second bank region being set to a normal mode.

公开(公告)号：US12250807B2

公开(公告)日：2025-03-11

申请号：US17496498

申请日：2021-10-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaesan Kim ,  Seunghan Woo ,  Haesuk Lee ,  Youngcheon Kwon ,  Reum Oh

IPC: H10B12/00 ,  H01L23/48 ,  H01L23/528 ,  H01L29/8605 ,  H01L29/94

Abstract: A semiconductor device includes a semiconductor structure including a semiconductor substrate having an active zone with a channel; a through silicon via (TSV) structure including a power TSV configured to transmit power and a signal TSV configured to transmit a signal; and a keep-out zone located a predetermined distance away from the TSV structure and bounded by the active zone. The TSV structure penetrates the semiconductor substrate. The keep-out zone includes a first element area a first distance away from the power TSV, and a second element area a second distance away from the signal TSV.

公开(公告)号：US11561711B2

公开(公告)日：2023-01-24

申请号：US17335307

申请日：2021-06-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngcheon Kwon ,  Jaesan Kim ,  Jemin Ryu ,  Jaeyoun Youn ,  Haesuk Lee

IPC: G06F3/06 ,  G11C7/10 ,  G11C7/22 ,  H01L25/18

Abstract: A memory device according to an aspect may include a memory cell array including a first bank region and a second bank region each including a plurality of banks; an operation logic including one or more first processing elements (PEs) corresponding to the first bank region and one or more second PEs corresponding to the second bank region; a control logic configured to control modes of the first bank region and the second bank region based on externally sourced setting information; first and second mode signal generators configured to control enabling the first PEs, wherein the first mode signal generator is configured to output the first mode signal to enable the first PEs and the second mode signal generator is configured to output the second mode signal to disable the second PEs responsive to the first bank region being set to an operation mode and the second bank region being set to a normal mode.