公开(公告)号：US11949012B2

公开(公告)日：2024-04-02

申请号：US17114598

申请日：2020-12-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong Ho Park ,  Wan Don Kim ,  Weon Hong Kim ,  Hyeon Jun Baek ,  Byoung Hoon Lee ,  Jeong Hyuk Yim ,  Sang Jin Hyun

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/78391 ,  H01L27/0886 ,  H01L29/4966 ,  H01L29/516

Abstract: A semiconductor device including: a first transistor which include a first gate stack on a substrate; and a second transistor which includes a second gate stack on the substrate, wherein the first gate stack includes a first ferroelectric material layer disposed on the substrate, a first work function layer disposed on the first ferroelectric material layer and a first upper gate electrode disposed on the first work function layer, wherein the second gate stack includes a second ferroelectric material layer disposed on the substrate, a second work function layer disposed on the second ferroelectric material layer and a second upper gate electrode disposed on the second work function layer, wherein the first work function layer includes the same material as the second work function layer, and wherein an effective work function of the first gate stack is different from an effective work function of the second gate stack.

公开(公告)号：US10770560B2

公开(公告)日：2020-09-08

申请号：US16214537

申请日：2018-12-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeong Hyuk Yim ,  Kug Hwan Kim ,  Wan Don Kim ,  Jung Min Park ,  Jong Ho Park ,  Byoung Hoon Lee ,  Yong Ho Ha ,  Sang Jin Hyun ,  Hye Ri Hong

IPC: H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L27/092 ,  H01L29/78 ,  H01L29/49

Abstract: A semiconductor device according to an example embodiment of the present inventive concept includes a substrate having a first region and a second region horizontally separate from the first region; a first gate line in the first region, the first gate line including a first lower work function layer and a first upper work function layer disposed on the first lower work function layer; and a second gate line including a second lower work function layer in the second region, the second gate line having a width in a first, horizontal direction equal to or narrower than a width of the first gate line in the first direction, wherein an uppermost end of the first upper work function layer and an uppermost end of the second lower work function layer are each located at a vertical level higher than an uppermost end of the first lower work function layer with respect to a second direction perpendicular to the first direction.

公开(公告)号：US20200176575A1

公开(公告)日：2020-06-04

申请号：US16695675

申请日：2019-11-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heon Bok Lee ,  Dae Yong Kim ,  Wan Don Kim ,  Jeong Hyuk Yim ,  Won Keun Chung ,  Hyo Seok Choi ,  Sang Jin Hyun

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768 ,  H01L29/08

Abstract: A semiconductor device includes an active pattern on a substrate, the active pattern extending in a first direction, a gate electrode on the active pattern, the gate electrode extending in a second direction intersecting the first direction and including a first portion and a second portion arranged along the second direction, a first contact plug on the gate electrode, the first contact plug being connected to a top surface of the second portion of the gate electrode, a source/drain region in the active pattern on a sidewall of the gate electrode, and a source/drain contact on the source/drain region, a height of a top surface of the source/drain contact being higher than a top surface of the first portion of the gate electrode and lower than the top surface of the second portion of the gate electrode.

公开(公告)号：US11322602B2

公开(公告)日：2022-05-03

申请号：US16794358

申请日：2020-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwi Chan Jun ,  Kang-Ill Seo ,  Jeong Hyuk Yim

IPC: H01L29/66 ,  H01L29/78

Abstract: Vertical field-effect transistor (VFET) devices and methods of forming VFET devices are provided. The methods may include forming a preliminary VFET on a substrate. The preliminary VFET may include a bottom source/drain region on the substrate, a channel region on the bottom source/drain region, a top source/drain region on the channel region, a patterned sacrificial layer on a side surface of the channel region, and an insulating layer. The top source/drain region and the patterned sacrificial layer may be enclosed by the insulating layer. The methods may also include forming a contact opening extending through the insulating layer and exposing a portion of the patterned sacrificial layer, forming a cavity between the channel region and the insulating layer by removing the patterned sacrificial layer through the contact opening, and forming a gate electrode in the cavity.

公开(公告)号：US11296196B2

公开(公告)日：2022-04-05

申请号：US16695675

申请日：2019-11-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heon Bok Lee ,  Dae Yong Kim ,  Wan Don Kim ,  Jeong Hyuk Yim ,  Won Keun Chung ,  Hyo Seok Choi ,  Sang Jin Hyun

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/08 ,  H01L21/768 ,  H01L29/78

Abstract: A semiconductor device includes an active pattern on a substrate, the active pattern extending in a first direction, a gate electrode on the active pattern, the gate electrode extending in a second direction intersecting the first direction and including a first portion and a second portion arranged along the second direction, a first contact plug on the gate electrode, the first contact plug being connected to a top surface of the second portion of the gate electrode, a source/drain region in the active pattern on a sidewall of the gate electrode, and a source/drain contact on the source/drain region, a height of a top surface of the source/drain contact being higher than a top surface of the first portion of the gate electrode and lower than the top surface of the second portion of the gate electrode.

公开(公告)号：US12087833B2

公开(公告)日：2024-09-10

申请号：US18380754

申请日：2023-10-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heon Bok Lee ,  Dae Yong Kim ,  Wan Don Kim ,  Jeong Hyuk Yim ,  Won Keun Chung ,  Hyo Seok Choi ,  Sang Jin Hyun

IPC: H01L29/417 ,  H01L21/768 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/41775 ,  H01L21/76897 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/6681 ,  H01L29/7851

Abstract: A semiconductor device includes an active pattern on a substrate, the active pattern extending in a first direction, a gate electrode on the active pattern, the gate electrode extending in a second direction intersecting the first direction and including a first portion and a second portion arranged along the second direction, a first contact plug on the gate electrode, the first contact plug being connected to a top surface of the second portion of the gate electrode, a source/drain region in the active pattern on a sidewall of the gate electrode, and a source/drain contact on the source/drain region, a height of a top surface of the source/drain contact being higher than a top surface of the first portion of the gate electrode and lower than the top surface of the second portion of the gate electrode.

公开(公告)号：US11799004B2

公开(公告)日：2023-10-24

申请号：US17694759

申请日：2022-03-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heon Bok Lee ,  Dae Yong Kim ,  Wan Don Kim ,  Jeong Hyuk Yim ,  Won Keun Chung ,  Hyo Seok Choi ,  Sang Jin Hyun

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/08 ,  H01L21/768 ,  H01L29/78

CPC classification number: H01L29/41775 ,  H01L21/76897 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/6681 ,  H01L29/7851

Abstract: A semiconductor device includes an active pattern on a substrate, the active pattern extending in a first direction, a gate electrode on the active pattern, the gate electrode extending in a second direction intersecting the first direction and including a first portion and a second portion arranged along the second direction, a first contact plug on the gate electrode, the first contact plug being connected to a top surface of the second portion of the gate electrode, a source/drain region in the active pattern on a sidewall of the gate electrode, and a source/drain contact on the source/drain region, a height of a top surface of the source/drain contact being higher than a top surface of the first portion of the gate electrode and lower than the top surface of the second portion of the gate electrode.