公开(公告)号：US11915982B2

公开(公告)日：2024-02-27

申请号：US17669452

申请日：2022-02-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwi Chan Jun ,  Min Gyu Kim

IPC: H01L21/8234

CPC classification number: H01L21/823487 ,  H01L21/823437 ,  H01L21/823481

Abstract: Vertical field-effect transistor (VFET) devices and methods of forming the same are provided. The methods may include forming a lower structure on a substrate. The lower structure may include first and second VFETs, a preliminary isolation structure between the first and second VFETs, and a gate liner on opposing sides of the preliminary isolation structure and between the preliminary isolation structure and the substrate. Each of the first and second VFETs may include a bottom source/drain region, a channel region and a top source/drain region sequentially stacked, and a gate structure on a side surface of the channel region. The preliminary isolation structure may include a sacrificial layer and a gap capping layer sequentially stacked. The methods may also include forming a top capping layer on the lower structure and then forming a cavity between the first and second VFETs by removing the sacrificial layer.

公开(公告)号：US11257913B2

公开(公告)日：2022-02-22

申请号：US16883308

申请日：2020-05-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hwi Chan Jun ,  Jung Ho Do

IPC: H01L29/417 ,  H01L27/092 ,  H01L29/423 ,  H01L29/78

Abstract: Provided is a structure of a vertical field effect transistor (VFET) device which includes: a fin structure protruding from a substrate, and having an H-shape in a plan view; a gate including a fin sidewall portion formed on sidewalls of the fin structure, and a field gate portion extended from the fin sidewall portion and filling a space inside a lower half of the fin structure; a gate contact landing on the field gate portion at a position inside the lower half of the fin structure; a bottom epitaxial layer comprising a bottom source/drain (S/D) region, and formed below the fin structure; a power contact landing on the bottom epitaxial layer, and configured to receive a power signal; a top S/D region formed above the fin structure; and a top S/D contact landing on the top S/D region.

公开(公告)号：US10340219B2

公开(公告)日：2019-07-02

申请号：US15868379

申请日：2018-01-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seul Ki Hong ,  Heon Jong Shin ,  Hwi Chan Jun ,  Min Chan Gwak

IPC: H01L29/66 ,  H01L21/321 ,  H01L23/485 ,  H01L21/3213 ,  H01L29/06 ,  H01L29/78 ,  H01L23/522 ,  H01L23/532 ,  H01L23/535 ,  H01L27/088

Abstract: A semiconductor device includes a substrate having a device isolation region defining an active region. An active fin is positioned in the active region. A gate structure overlaps the active fin along a direction orthogonal to an upper surface of the substrate and extends in a second direction intersecting the first direction. A source/drain region is disposed on the active fin. A contact plug is connected to the source/drain region and overlaps the active fin. A metal via is positioned at a first level above the substrate higher than an upper surface of the contact plug and spaced apart from the active fin. A metal line is positioned at a second level above the substrate, higher than the first level and connected to the metal via. A via connection layer extends from an upper portion of the contact plug and is connected to the metal via.

公开(公告)号：US11538924B2

公开(公告)日：2022-12-27

申请号：US17026453

申请日：2020-09-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hwi Chan Jun ,  Min Gyu Kim ,  Gil-Hwan Son

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L21/285

Abstract: A vertical field effect transistor (VFET) device and a method of manufacturing the same are provided. The method includes: (a) providing an intermediate VFET structure comprising a substrate, and fin structures, gate structures and bottom epitaxial layers on the substrate, the gate structures being formed on the fin structures, respectively, each fin structure comprising a fin and a mask thereon, and the bottom epitaxial layers; (b) filling interlayer dielectric (ILD) layers between and at sides of the gate structures; (c) forming an ILD protection layer on the ILD layers, respectively, the ILD protection layer having upper portions and lower portions, and comprising a material preventing oxide loss at the ILD layers; (d) removing the fin structures, the gate structures and the ILD protection layer above the lower portion of the ILD protection layer; (e) removing the masks of the fin structures and top portions of the gate structures so that top surfaces of the fin structures and top surfaces of the gate structures after the removing are lower than top surfaces of the ILD layers; (f) forming top spacers on the gate structures of which the top portions are removed, and top epitaxial layers on the fin structures of which the masks are removed; and (g) forming a contact structure connected to the top epitaxial layers.

公开(公告)号：US20220165623A1

公开(公告)日：2022-05-26

申请号：US17669452

申请日：2022-02-11

Applicant: Samsung Electronics Co., Ltd

Inventor： Hwi Chan Jun ,  Min Gyu Kim

IPC: H01L21/8234

Abstract: Vertical field-effect transistor (VFET) devices and methods of forming the same are provided. The methods may include forming a lower structure on a substrate. The lower structure may include first and second VFETs, a preliminary isolation structure between the first and second VFETs, and a gate liner on opposing sides of the preliminary isolation structure and between the preliminary isolation structure and the substrate. Each of the first and second VFETs may include a bottom source/drain region, a channel region and a top source/drain region sequentially stacked, and a gate structure on a side surface of the channel region. The preliminary isolation structure may include a sacrificial layer and a gap capping layer sequentially stacked. The methods may also include forming a top capping layer on the lower structure and then forming a cavity between the first and second VFETs by removing the sacrificial layer.

公开(公告)号：US11094593B2

公开(公告)日：2021-08-17

申请号：US16169326

申请日：2018-10-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hwi Chan Jun ,  Chang Hwa Kim ,  Dae Won Ha

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L23/522 ,  H01L21/8238

Abstract: A semiconductor device including a contact structure is provided. The semiconductor device includes an isolation region defining a lower active region. First and second source/drain regions and first and second gate electrodes are on the lower active region. The first and second source/drain regions are adjacent to each other. First and second gate capping patterns are on the first and second gate electrodes, respectively. First and second contact structures are on the first and second source/drain regions, respectively. A lower insulating pattern is between the first and second source/drain regions. An upper insulating pattern is between the first and second contact structures. Silicon oxide has etching selectivity with respect to an insulating material which the upper insulating pattern, the first gate capping pattern, and the second gate capping pattern are formed of.

公开(公告)号：US12218010B2

公开(公告)日：2025-02-04

申请号：US18418795

申请日：2024-01-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwi Chan Jun ,  Min Gyu Kim

IPC: H01L21/8234 ,  H01L29/792

Abstract: Vertical field-effect transistor (VFET) devices and methods of forming the same are provided. The methods may include forming a lower structure on a substrate. The lower structure may include first and second VFETs, a preliminary isolation structure between the first and second VFETs, and a gate liner on opposing sides of the preliminary isolation structure and between the preliminary isolation structure and the substrate. Each of the first and second VFETs may include a bottom source/drain region, a channel region and a top source/drain region sequentially stacked, and a gate structure on a side surface of the channel region. The preliminary isolation structure may include a sacrificial layer and a gap capping layer sequentially stacked. The methods may also include forming a top capping layer on the lower structure and then forming a cavity between the first and second VFETs by removing the sacrificial layer.

公开(公告)号：US11721581B2

公开(公告)日：2023-08-08

申请号：US17031279

申请日：2020-09-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min Chan Gwak ,  Hwi Chan Jun ,  Heon Jong Shin ,  So Ra You ,  Sang Hyun Lee ,  In Chan Hwang

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L29/45 ,  H01L29/775

CPC classification number: H01L21/76897 ,  H01L23/528 ,  H01L23/5226 ,  H01L23/5283 ,  H01L29/41775 ,  H01L29/41791 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/456 ,  H01L29/775 ,  H01L29/785

Abstract: A semiconductor device includes active regions, a gate electrode, respective drain regions, respective source regions, a drain contact structure, a source contact structure, and a gate contact structure. The active regions extend linearly in parallel on a substrate. The gate electrode crosses the active regions. The drain regions are on and/or in the active regions on a first side of the gate electrode. The respective source regions are on and/or in the active regions on a second side of the gate electrode. The drain contact structure is on multiple drain regions. The source contact structure is on multiple source regions. The gate contact structure is on the gate electrode between the drain and source contact structures. The gate contact structure includes a gate plug and an upper gate plug directly on the gate plug. A center of the gate contact structure overlies only one of the active regions.

公开(公告)号：US20180358293A1

公开(公告)日：2018-12-13

申请号：US15868379

申请日：2018-01-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seul Ki HONG ,  Heon Jong Shin ,  Hwi Chan Jun ,  Min Chan Gwak

IPC: H01L23/522 ,  H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L23/535 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/32115 ,  H01L21/32137 ,  H01L23/485 ,  H01L23/53257 ,  H01L23/53261 ,  H01L23/53295 ,  H01L23/535 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/7851

Abstract: A semiconductor device includes a substrate having a device isolation region defining an active region. An active fin is positioned in the active region. A gate structure overlaps the active fin along a direction orthogonal to an upper surface of the substrate and extends in a second direction intersecting the first direction, A source/drain region is disposed on the active fin. A contact plug is connected to the source/drain region and overlaps the active fin. A metal via is positioned at a first level above the substrate higher than an upper surface of the contact plug and spaced apart from the active fin. A metal line is positioned at a second level above the substrate, higher than the first level and connected to the metal via. A via connection layer extends from an upper portion of the contact plug and is connected to the metal via.

公开(公告)号：US10153212B2

公开(公告)日：2018-12-11

申请号：US15449302

申请日：2017-03-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hwi Chan Jun ,  Chang Hwa Kim ,  Dae Won Ha

IPC: H01L27/088 ,  H01L21/8234 ,  H01L23/522

Abstract: A semiconductor device including a contact structure is provided. The semiconductor device includes an isolation region defining a lower active region. First and second source/drain regions and first and second gate electrodes are on the lower active region. The first and second source/drain regions are adjacent to each other. First and second gate capping patterns are on the first and second gate electrodes, respectively. First and second contact structures are on the first and second source/drain regions, respectively. A lower insulating pattern is between the first and second source/drain regions. An upper insulating pattern is between the first and second contact structures. Silicon oxide has etching selectivity with respect to an insulating material which the upper insulating pattern, the first gate capping pattern, and the second gate capping pattern are formed of.