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公开(公告)号：US20190148456A1
公开(公告)日：2019-05-16
申请号：US16226855
申请日：2018-12-20
Applicant: Samsung Electronics Co., Ltd.
Inventor： Zhe Wu , Dong-ho Ahn , Hideki Horii , Soon-oh Park , Jeong-hee Park , Jin-woo Lee , Dong-jun Seong , Seol Choi
CPC classification number: H01L27/2481 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/143 , H01L45/144 , H01L45/1675
Abstract: A memory device includes a plurality of word lines extending along a first direction and spaced apart from each other along a second direction that is perpendicular to the first direction; a plurality of bit lines extending along the second direction and spaced apart from each other in the first direction, the plurality of bit lines being spaced apart from the plurality of word lines in a third direction that is perpendicular to both the first and second directions; and a plurality of memory cells being respectively arranged between the corresponding word and bit lines. Each of the memory cells includes a selection device layer, and a variable resistance layer, wherein the selection device layer includes a chalcogenide switching material having a composition according to a particular chemical formula.
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公开(公告)号：US10224371B2
公开(公告)日：2019-03-05
申请号：US15421498
申请日：2017-02-01
Applicant: Samsung Electronics Co., Ltd.
Inventor： Zhe Wu , Dong-ho Ahn , Hideki Horii , Soon-oh Park , Jeong-hee Park , Jin-woo Lee , Dong-jun Seong , Seol Choi
Abstract: A memory device includes a variable resistance layer and a selection device layer electrically connected to the variable resistance layer. The memory device further included a chalcogenide switching material that reduces leakage current and has, for example, a composition according to chemical formula 1 below, [GeXSiY(AsaTe1-a)Z](1-U)[N]U (1) (where 0.05≤X≤0.1, 0.15≤Y≤0.25, 0.7≤Z≤0.8, X+Y+Z=1, 0.45≤a≤0.6, and 0.08≤U≤0.2).
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公开(公告)号：US20160372359A1
公开(公告)日：2016-12-22
申请号：US15065916
申请日：2016-03-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Myung-ho Kong , Jeong-hee Park , Taek-jung Kim , Han-young Kim , Keon-seok Seo , Jong-myeong Lee , Hee-sook Park
IPC: H01L21/768 , H01L21/28
CPC classification number: H01L21/743 , H01L21/76897 , H01L27/10876 , H01L27/10885 , H01L27/10894 , H01L29/4236 , H01L29/78
Abstract: A method of fabricating a semiconductor device includes forming a doped polysilicon layer on a substrate, forming a barrier layer on the doped polysilicon layer, forming an oxidized barrier layer by oxidizing a surface of the barrier layer, and forming a metal layer on the oxidized barrier layer.
Abstract translation: 制造半导体器件的方法包括在衬底上形成掺杂多晶硅层，在掺杂多晶硅层上形成阻挡层，通过氧化势垒层表面形成氧化阻挡层，并在氧化势垒上形成金属层 层。
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Patent Agency Ranking
公开(公告)号：US20200052038A1
公开(公告)日：2020-02-13
申请号：US16277385
申请日：2019-02-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Byongju Kim , Young-min Ko , Jong-uk Kim , Kwangmin Park , Jeong-hee Park
Abstract: There is provided a variable resistance memory device including a first electrode line layer including first electrode lines extending in a first direction and spaced apart from each other on a substrate, a second electrode line layer that is above the first electrode line layer and including second electrode lines extending in a second direction orthogonal to the first direction and spaced apart from each other, and a memory cell layer including memory cells between the first electrode line layer and the second electrode line layer. Each of the memory cells includes a selection device layer, an intermediate electrode layer, and a variable resistance layer. A first insulating layer is between the first electrode lines, a second insulating layer is between the memory cells, and a third insulating layer is between the second electrode lines. The second insulating layer includes air gaps on side surfaces of the memory cells.
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公开(公告)号：US20180026077A1
公开(公告)日：2018-01-25
申请号：US15421498
申请日：2017-02-01
Applicant: Samsung Electronics Co., Ltd.
Inventor： Zhe Wu , Dong-ho Ahn , Hideki Horii , Soon-oh Park , Jeong-hee Park , Jin-woo Lee , Dong-jun Seong , Seol Choi
CPC classification number: H01L27/2481 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/143 , H01L45/144 , H01L45/1675
Abstract: A memory device includes a variable resistance layer and a selection device layer electrically connected to the variable resistance layer. The memory device further included a chalcogenide switching material that reduces leakage current and has, for example, a composition according to chemical formula 1 below, [GeXSiY(AsaTe1-a)Z](1-U)[N]U (1) (where 0.05≦X≦0.1, 0.15≦Y≦0.25, 0.7≦Z≦0.8, X+Y+Z=1, 0.45≦a≦0.6, and 0.08≦U≦0.2).
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公开(公告)号：US09875925B2
公开(公告)日：2018-01-23
申请号：US15065916
申请日：2016-03-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Myung-ho Kong , Jeong-hee Park , Taek-jung Kim , Han-young Kim , Keon-seok Seo , Jong-myeong Lee , Hee-sook Park
IPC: H01L21/74 , H01L29/423 , H01L29/78 , H01L21/768
CPC classification number: H01L21/743 , H01L21/76897 , H01L27/10876 , H01L27/10885 , H01L27/10894 , H01L29/4236 , H01L29/78
Abstract: A method of fabricating a semiconductor device includes forming a doped polysilicon layer on a substrate, forming a barrier layer on the doped polysilicon layer, forming an oxidized barrier layer by oxidizing a surface of the barrier layer, and forming a metal layer on the oxidized barrier layer.
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公开(公告)号：US10720470B2
公开(公告)日：2020-07-21
申请号：US16277385
申请日：2019-02-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Byongju Kim , Young-min Ko , Jong-uk Kim , Kwangmin Park , Jeong-hee Park
Abstract: There is provided a variable resistance memory device including a first electrode line layer including first electrode lines extending in a first direction and spaced apart from each other on a substrate, a second electrode line layer that is above the first electrode line layer and including second electrode lines extending in a second direction orthogonal to the first direction and spaced apart from each other, and a memory cell layer including memory cells between the first electrode line layer and the second electrode line layer. Each of the memory cells includes a selection device layer, an intermediate electrode layer, and a variable resistance layer. A first insulating layer is between the first electrode lines, a second insulating layer is between the memory cells, and a third insulating layer is between the second electrode lines. The second insulating layer includes air gaps on side surfaces of the memory cells.
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公开(公告)号：US10546894B2
公开(公告)日：2020-01-28
申请号：US16226855
申请日：2018-12-20
Applicant: Samsung Electronics Co., Ltd.
Inventor： Zhe Wu , Dong-ho Ahn , Hideki Horii , Soon-oh Park , Jeong-hee Park , Jin-woo Lee , Dong-jun Seong , Seol Choi
Abstract: A memory device includes a plurality of word lines extending along a first direction and spaced apart from each other along a second direction that is perpendicular to the first direction; a plurality of bit lines extending along the second direction and spaced apart from each other in the first direction, the plurality of bit lines being spaced apart from the plurality of word lines in a third direction that is perpendicular to both the first and second directions; and a plurality of memory cells being respectively arranged between the corresponding word and bit lines. Each of the memory cells includes a selection device layer, and a variable resistance layer, wherein the selection device layer includes a chalcogenide switching material having a composition according to a particular chemical formula.
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