公开(公告)号：US20240347510A1

公开(公告)日：2024-10-17

申请号：US18585468

申请日：2024-02-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeongil Lee ,  Byeongchan Kim ,  Unbyoung Kang ,  Jumyong Park

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L23/49822 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/03616 ,  H01L2224/05647 ,  H01L2224/13027 ,  H01L2224/81895 ,  H01L2225/06541 ,  H01L2924/1436

Abstract: A semiconductor package includes a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first semiconductor chip includes a plurality of through electrodes, first bonding pads provided on a first surface of a first substrate, a first passivation layer provided on the first surface and exposing the first bonding pads, a polishing stop layer pattern provided on a second surface of the first substrate and exposing end portions of the plurality of through electrodes, and second bonding pads provided on the polishing stop layer pattern. The second semiconductor chip includes third bonding pads provided on a first surface of a second substrate, and a second passivation layer provided on the first surface of the second substrate and exposing the third bonding pads. The first bonding pads and the third bonding pads are directly bonded to each other.