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公开(公告)号：US20240347510A1
公开(公告)日：2024-10-17
申请号：US18585468
申请日：2024-02-23
发明人： Jeongil Lee , Byeongchan Kim , Unbyoung Kang , Jumyong Park
IPC分类号： H01L25/065 , H01L23/00 , H01L23/48 , H01L23/498
CPC分类号： H01L25/0657 , H01L23/481 , H01L23/49822 , H01L24/03 , H01L24/05 , H01L24/13 , H01L24/81 , H01L2224/03616 , H01L2224/05647 , H01L2224/13027 , H01L2224/81895 , H01L2225/06541 , H01L2924/1436
摘要： A semiconductor package includes a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first semiconductor chip includes a plurality of through electrodes, first bonding pads provided on a first surface of a first substrate, a first passivation layer provided on the first surface and exposing the first bonding pads, a polishing stop layer pattern provided on a second surface of the first substrate and exposing end portions of the plurality of through electrodes, and second bonding pads provided on the polishing stop layer pattern. The second semiconductor chip includes third bonding pads provided on a first surface of a second substrate, and a second passivation layer provided on the first surface of the second substrate and exposing the third bonding pads. The first bonding pads and the third bonding pads are directly bonded to each other.
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公开(公告)号：US12119306B2
公开(公告)日：2024-10-15
申请号：US18307277
申请日：2023-04-26
发明人： Ju-Il Choi , Gyuho Kang , Un-Byoung Kang , Byeongchan Kim , Junyoung Park , Jongho Lee , Hyunsu Hwang
IPC分类号： H01L23/538 , H01L23/00 , H01L23/31 , H01L23/498 , H01L25/10
CPC分类号： H01L23/5389 , H01L23/3128 , H01L23/49811 , H01L23/49822 , H01L23/49838 , H01L23/5383 , H01L24/16 , H01L25/105 , H01L2224/16225
摘要： A semiconductor package including a redistribution substrate including an insulating layer and redistribution patterns in the insulating layer may be provided. Each of the redistribution patterns may include a via portion, a pad portion vertically overlapping the via portion, and a line portion extending from the pad portion. The via portion, the pad portion, and the line portion may be connected to each other to form a single object. A level of a bottom surface of the pad portion may be lower than a level of a bottom surface of the line portion. A width of the line portion may have a largest value at a level between a top surface of the line portion and the bottom surface of the line portion.
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公开(公告)号：US12021034B2
公开(公告)日：2024-06-25
申请号：US17198359
申请日：2021-03-11
发明人： Solji Song , Byeongchan Kim , Jumyong Park , Jinho An , Chungsun Lee , Jeonggi Jin , Juil Choi
IPC分类号： H01L23/538 , H01L23/00 , H01L25/065
CPC分类号： H01L23/5386 , H01L23/5383 , H01L24/16 , H01L25/0655 , H01L2224/16227
摘要： A semiconductor package includes an interposer having a first surface and a second surface opposite to the first surface and including a plurality of bonding pads, and first and second semiconductor devices on the interposer. Each of the plurality of bonding pads includes a first pad pattern provided to be exposed from the first surface and having a first width and a second pad pattern provided on the first pad pattern and having a second width greater than the first width.
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公开(公告)号：US20230260923A1
公开(公告)日：2023-08-17
申请号：US18307277
申请日：2023-04-26
发明人： Ju-Il CHOI , Gyuho Kang , Un-Byoung Kang , Byeongchan Kim , Junyoung Park , Jongho Lee , Hyunsu Hwang
IPC分类号： H01L23/538 , H01L23/498 , H01L23/00 , H01L23/31 , H01L25/10
CPC分类号： H01L23/5389 , H01L23/49822 , H01L23/49811 , H01L23/49838 , H01L24/16 , H01L23/3128 , H01L25/105 , H01L23/5383 , H01L2224/16225
摘要： A semiconductor package including a redistribution substrate including an insulating layer and redistribution patterns in the insulating layer may be provided. Each of the redistribution patterns may include a via portion, a pad portion vertically overlapping the via portion, and a line portion extending from the pad portion. The via portion, the pad portion, and the line portion may be connected to each other to form a single object. A level of a bottom surface of the pad portion may be lower than a level of a bottom surface of the line portion. A width of the line portion may have a largest value at a level between a top surface of the line portion and the bottom surface of the line portion.
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公开(公告)号：US11682630B2
公开(公告)日：2023-06-20
申请号：US17349174
申请日：2021-06-16
发明人： Ju-Il Choi , Gyuho Kang , Un-Byoung Kang , Byeongchan Kim , Junyoung Park , Jongho Lee , Hyunsu Hwang
IPC分类号： H01L23/538 , H01L23/498 , H01L23/00 , H01L23/31 , H01L25/10
CPC分类号： H01L23/5389 , H01L23/3128 , H01L23/49811 , H01L23/49822 , H01L23/49838 , H01L23/5383 , H01L24/16 , H01L25/105 , H01L2224/16225
摘要： A semiconductor package including a redistribution substrate including an insulating layer and redistribution patterns in the insulating layer may be provided. Each of the redistribution patterns may include a via portion, a pad portion vertically overlapping the via portion, and a line portion extending from the pad portion. The via portion, the pad portion, and the line portion may be connected to each other to form a single object. A level of a bottom surface of the pad portion may be lower than a level of a bottom surface of the line portion. A width of the line portion may have a largest value at a level between a top surface of the line portion and the bottom surface of the line portion.
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