公开(公告)号：US20240347510A1

公开(公告)日：2024-10-17

申请号：US18585468

申请日：2024-02-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeongil Lee ,  Byeongchan Kim ,  Unbyoung Kang ,  Jumyong Park

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L23/49822 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/03616 ,  H01L2224/05647 ,  H01L2224/13027 ,  H01L2224/81895 ,  H01L2225/06541 ,  H01L2924/1436

Abstract: A semiconductor package includes a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first semiconductor chip includes a plurality of through electrodes, first bonding pads provided on a first surface of a first substrate, a first passivation layer provided on the first surface and exposing the first bonding pads, a polishing stop layer pattern provided on a second surface of the first substrate and exposing end portions of the plurality of through electrodes, and second bonding pads provided on the polishing stop layer pattern. The second semiconductor chip includes third bonding pads provided on a first surface of a second substrate, and a second passivation layer provided on the first surface of the second substrate and exposing the third bonding pads. The first bonding pads and the third bonding pads are directly bonded to each other.

公开(公告)号：US12199056B2

公开(公告)日：2025-01-14

申请号：US17726363

申请日：2022-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jumyong Park ,  Unbyoung Kang ,  Byeongchan Kim ,  Solji Song ,  Chungsun Lee

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor package includes a first semiconductor chip having a first substrate, a first insulating layer on the first substrate, and a plurality of first bonding pads on the first insulating layer, and having a flat upper surface by an upper surface of the first insulating layer and upper surfaces of the plurality of first bonding pads; and a second semiconductor chip on the upper surface of the first semiconductor chip and having a second substrate, a second insulating layer below the second substrate and in contact with the first insulating layer, and a plurality of second bonding pads on the second insulating layer and in contact with the first bonding pads, respectively, wherein the first insulating layer includes an insulating interfacial layer in contact with the second insulating layer, embedded in the first insulating layer, and spaced apart from the plurality of first bonding pads.

公开(公告)号：US12119306B2

公开(公告)日：2024-10-15

申请号：US18307277

申请日：2023-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Il Choi ,  Gyuho Kang ,  Un-Byoung Kang ,  Byeongchan Kim ,  Junyoung Park ,  Jongho Lee ,  Hyunsu Hwang

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/10

CPC classification number: H01L23/5389 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5383 ,  H01L24/16 ,  H01L25/105 ,  H01L2224/16225

Abstract: A semiconductor package including a redistribution substrate including an insulating layer and redistribution patterns in the insulating layer may be provided. Each of the redistribution patterns may include a via portion, a pad portion vertically overlapping the via portion, and a line portion extending from the pad portion. The via portion, the pad portion, and the line portion may be connected to each other to form a single object. A level of a bottom surface of the pad portion may be lower than a level of a bottom surface of the line portion. A width of the line portion may have a largest value at a level between a top surface of the line portion and the bottom surface of the line portion.

公开(公告)号：US12021034B2

公开(公告)日：2024-06-25

申请号：US17198359

申请日：2021-03-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Solji Song ,  Byeongchan Kim ,  Jumyong Park ,  Jinho An ,  Chungsun Lee ,  Jeonggi Jin ,  Juil Choi

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/5386 ,  H01L23/5383 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16227

Abstract: A semiconductor package includes an interposer having a first surface and a second surface opposite to the first surface and including a plurality of bonding pads, and first and second semiconductor devices on the interposer. Each of the plurality of bonding pads includes a first pad pattern provided to be exposed from the first surface and having a first width and a second pad pattern provided on the first pad pattern and having a second width greater than the first width.

公开(公告)号：US20230260923A1

公开(公告)日：2023-08-17

申请号：US18307277

申请日：2023-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Il CHOI ,  Gyuho Kang ,  Un-Byoung Kang ,  Byeongchan Kim ,  Junyoung Park ,  Jongho Lee ,  Hyunsu Hwang

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10

CPC classification number: H01L23/5389 ,  H01L23/49822 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/16 ,  H01L23/3128 ,  H01L25/105 ,  H01L23/5383 ,  H01L2224/16225

Abstract: A semiconductor package including a redistribution substrate including an insulating layer and redistribution patterns in the insulating layer may be provided. Each of the redistribution patterns may include a via portion, a pad portion vertically overlapping the via portion, and a line portion extending from the pad portion. The via portion, the pad portion, and the line portion may be connected to each other to form a single object. A level of a bottom surface of the pad portion may be lower than a level of a bottom surface of the line portion. A width of the line portion may have a largest value at a level between a top surface of the line portion and the bottom surface of the line portion.

公开(公告)号：US11682630B2

公开(公告)日：2023-06-20

申请号：US17349174

申请日：2021-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Il Choi ,  Gyuho Kang ,  Un-Byoung Kang ,  Byeongchan Kim ,  Junyoung Park ,  Jongho Lee ,  Hyunsu Hwang

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10

CPC classification number: H01L23/5389 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5383 ,  H01L24/16 ,  H01L25/105 ,  H01L2224/16225

Abstract: A semiconductor package including a redistribution substrate including an insulating layer and redistribution patterns in the insulating layer may be provided. Each of the redistribution patterns may include a via portion, a pad portion vertically overlapping the via portion, and a line portion extending from the pad portion. The via portion, the pad portion, and the line portion may be connected to each other to form a single object. A level of a bottom surface of the pad portion may be lower than a level of a bottom surface of the line portion. A width of the line portion may have a largest value at a level between a top surface of the line portion and the bottom surface of the line portion.