公开(公告)号：US20240047396A1

公开(公告)日：2024-02-08

申请号：US17882416

申请日：2022-08-05

Applicant: Micron Technology, Inc.

Inventor： Thiagarajan Raman

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/08 ,  H01L25/0657 ,  H01L24/16 ,  H01L24/73 ,  H01L24/32 ,  H01L24/05 ,  H01L24/81 ,  H01L24/13 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06527 ,  H01L2225/06589 ,  H01L2224/81203 ,  H01L2224/8183 ,  H01L2224/81895 ,  H01L2224/80896 ,  H01L2224/05687 ,  H01L2224/13147 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/16145 ,  H01L2224/08145 ,  H01L2924/3511 ,  H01L2924/182 ,  H01L2224/16225 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/1431

Abstract: This document discloses techniques, apparatuses, and systems for a bonded semiconductor device. A semiconductor assembly is described that includes a first semiconductor die having a first surface and a second semiconductor die having a second surface. A first electrical contact coupled to the first semiconductor die protrudes from the first surface and couples, through a solder joint, to a second electrical contact that couples to the second semiconductor die and protrudes from the second surface. A first non-conductive bonding structure protrudes from the first surface and couples to a second non-conductive bonding structure that protrudes from the second surface.

公开(公告)号：US11728326B2

公开(公告)日：2023-08-15

申请号：US17115143

申请日：2020-12-08

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Ziqi Chen ,  Chao Li ,  Guanping Wu

IPC: H01L27/11575 ,  H01L25/00 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/91 ,  H01L25/0657 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/81895 ,  H01L2224/83896 ,  H01L2924/01014 ,  H01L2924/14511

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the method for forming a memory device includes the following operations. First, a plurality of first semiconductor channels can be formed over a first wafer with a peripheral device and a plurality of first via structures neighboring the plurality of first semiconductor channels. The plurality of first semiconductor channels can extend along a direction perpendicular to a surface of the first wafer. Further, a plurality of second semiconductor channels can be formed over a second wafer with a plurality of second via structures neighboring the plurality of second semiconductor channels. The plurality of second semiconductor channels can extend along a direction perpendicular to a surface of the second wafer and a peripheral via structure.

公开(公告)号：US20230253395A1

公开(公告)日：2023-08-10

申请号：US18302063

申请日：2023-04-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Jie Chen

IPC: H01L25/00 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L23/498 ,  H01L21/48 ,  H01L21/683 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18

CPC classification number: H01L25/50 ,  H01L24/02 ,  H01L24/09 ,  H01L23/3107 ,  H01L24/73 ,  H01L24/81 ,  H01L21/568 ,  H01L23/49811 ,  H01L21/4853 ,  H01L24/03 ,  H01L21/6835 ,  H01L24/92 ,  H01L24/96 ,  H01L21/6836 ,  H01L25/0657 ,  H01L25/10 ,  H01L25/18 ,  H01L25/065 ,  H01L25/105 ,  H01L21/4846 ,  H01L21/486 ,  H01L21/565 ,  H01L24/48 ,  H01L2224/02331 ,  H01L2224/02373 ,  H01L2224/0905 ,  H01L2224/48137 ,  H01L2224/13008 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2224/45144 ,  H01L23/3114 ,  H01L23/3128 ,  H01L21/561 ,  H01L2224/0401 ,  H01L2224/48091 ,  H01L23/49816 ,  H01L23/49822 ,  H01L2224/13084 ,  H01L2224/81895 ,  H01L2224/13311 ,  H01L2224/13181 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/03003 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/06181 ,  H01L2224/1132 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/13021 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13294 ,  H01L2224/133 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/48227 ,  H01L2224/81005 ,  H01L2224/81024 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81411 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2224/92 ,  H01L2224/96 ,  H01L2224/13166 ,  H01L2221/68327 ,  H01L2221/68345 ,  H01L2221/68372 ,  H01L2224/45147 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/3511 ,  H01L2224/2518 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2224/451 ,  H01L21/304

Abstract: Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a semiconductor package including a first package including one or more dies, and a redistribution layer coupled to the one or more dies at a first side of the first package with a first set of bonding joints. The redistribution layer including more than one metal layer disposed in more than one passivation layer, the first set of bonding joints being directly coupled to at least one of the one or more metal layers, and a first set of connectors coupled to a second side of the redistribution layer, the second side being opposite the first side.

公开(公告)号：US11705425B2

公开(公告)日：2023-07-18

申请号：US17301843

申请日：2021-04-15

Applicant: Micron Technology, Inc.

Inventor： Benjamin L. McClain ,  Brandon P. Wirz ,  Zhaohui Ma

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L24/75 ,  H01L21/4853 ,  H01L21/563 ,  H01L24/27 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/13 ,  H01L24/16 ,  H01L24/94 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/27003 ,  H01L2224/2783 ,  H01L2224/2784 ,  H01L2224/27436 ,  H01L2224/32013 ,  H01L2224/32058 ,  H01L2224/32059 ,  H01L2224/32105 ,  H01L2224/32106 ,  H01L2224/32225 ,  H01L2224/73103 ,  H01L2224/73204 ,  H01L2224/7532 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/75303 ,  H01L2224/75312 ,  H01L2224/75318 ,  H01L2224/75745 ,  H01L2224/8182 ,  H01L2224/81169 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/81895 ,  H01L2224/83203 ,  H01L2224/83862 ,  H01L2224/9211 ,  H01L2224/9212 ,  H01L2224/94 ,  H01L2924/00012 ,  H01L2224/94 ,  H01L2224/27 ,  H01L2224/94 ,  H01L2224/11 ,  H01L2224/9212 ,  H01L2224/11 ,  H01L2224/27 ,  H01L2224/9211 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/81169 ,  H01L2924/00014 ,  H01L2224/2783 ,  H01L2924/00012

Abstract: A bond tip for thermocompression bonding a bottom surface includes a die contact area and a low surface energy material covering at least a portion of the bottom surface. The low surface energy material may cover substantially all of the bottom surface, or only a peripheral portion surrounding the die contact area. The die contact area may be recessed with respect to the peripheral portion a depth at least as great as a thickness of a semiconductor die to be received in the recessed die contact area. A method of thermocompression bonding is also disclosed.

公开(公告)号：US20180138164A1

公开(公告)日：2018-05-17

申请号：US15705427

申请日：2017-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho Jin LEE ,  Seok Ho Kim ,  Kwang Jin Moon ,  Byung Lyul Park ,  Nae In Lee

IPC: H01L25/00 ,  H01L23/00 ,  H01L21/3065 ,  H01L21/768 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3083 ,  H01L21/67 ,  H01L21/76898 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/89 ,  H01L24/92 ,  H01L25/0657 ,  H01L2224/08145 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/81895 ,  H01L2224/81896 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/00

Abstract: There is provided a method for fabricating a substrate structure capable of enhancing process reproducibility and process stability by trimming a bevel region of a substrate using a wafer level process. The method includes providing a first substrate including first and second surfaces opposite each other and a first device region formed at the first surface, providing a second substrate including third and fourth surfaces opposite each other and a second device region at the third surface, bonding the first substrate and the second substrate to electrically connect the first device region and the second device region, and forming a trimmed substrate. The forming the trimmed substrate includes etching an edge region of the second substrate bonded to the first substrate.

公开(公告)号：US09905530B2

公开(公告)日：2018-02-27

申请号：US15449466

申请日：2017-03-03

Applicant: Kulicke and Soffa Industries, Inc.

Inventor： Robert N. Chylak ,  Dominick A. DeAngelis

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/10 ,  H01L25/065

CPC classification number: H01L24/81 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/48 ,  H01L24/75 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13624 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/75301 ,  H01L2224/75343 ,  H01L2224/75348 ,  H01L2224/75349 ,  H01L2224/75744 ,  H01L2224/75745 ,  H01L2224/759 ,  H01L2224/8112 ,  H01L2224/81121 ,  H01L2224/81193 ,  H01L2224/81201 ,  H01L2224/81203 ,  H01L2224/81205 ,  H01L2224/81207 ,  H01L2224/81409 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/818 ,  H01L2224/81801 ,  H01L2224/81895 ,  H01L2224/81906 ,  H01L2225/06513 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/20102 ,  H01L2924/20103 ,  H01L2924/20104 ,  H01L2924/20105 ,  H01L2924/20106 ,  H01L2924/20107 ,  H01L2924/20301 ,  H01L2924/20302 ,  H01L2924/20303 ,  H01L2924/20304 ,  H01L2924/20305 ,  H01L2924/20306 ,  H01L2924/20307 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01014 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/8121 ,  H01L2924/00

Abstract: A method of ultrasonically bonding semiconductor elements includes the steps of: (a) aligning surfaces of a plurality of first conductive structures of a first semiconductor element to respective surfaces of a plurality of second conductive structures of a second semiconductor element, wherein the surfaces of each of the plurality of first conductive structures and the plurality of second conductive structures include aluminum; and (b) ultrasonically bonding ones of the first conductive structures to respective ones of the second conductive structures.

公开(公告)号：US09881888B2

公开(公告)日：2018-01-30

申请号：US15083085

申请日：2016-03-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Meng-Tse Chen ,  Hsiu-Jen Lin ,  Chih-Wei Lin ,  Ming-Da Cheng ,  Chih-Hang Tung ,  Chung-Shi Liu

IPC: H01L21/44 ,  H01L23/00 ,  H01L25/10 ,  H01L21/56 ,  H01L25/00

CPC classification number: H01L24/06 ,  H01L21/56 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/0558 ,  H01L2224/05666 ,  H01L2224/1134 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11825 ,  H01L2224/119 ,  H01L2224/11906 ,  H01L2224/13005 ,  H01L2224/13014 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/16058 ,  H01L2224/16238 ,  H01L2224/16501 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81895 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A conductive interconnect structure includes a contact pad; a conductive body connected to the contact pad at a first end; and a conductive layer positioned on a second end of the conductive body. The conductive body has a longitudinal direction perpendicular to a surface of the contact pad. The conductive body has an average grain size (a) on a cross sectional plane (Plane A) whose normal is perpendicular to the longitudinal direction of the conductive body. The conductive layer has an average grain size (b) on Plane A. The conductive body and the conductive layer are composed of same material, and the average grain size (a) is greater than the average grain size (b).

公开(公告)号：US20170345786A1

公开(公告)日：2017-11-30

申请号：US15254758

申请日：2016-09-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ying-Ju Chen ,  An-Jhih Su ,  Hsien-Wei Chen ,  Der-Chyang Yeh ,  Chi-Hsi Wu ,  Chen-Hua Yu

IPC: H01L23/00

CPC classification number: H01L24/32 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/20 ,  H01L24/27 ,  H01L24/29 ,  H01L24/48 ,  H01L24/81 ,  H01L24/83 ,  H01L25/105 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04105 ,  H01L2224/05017 ,  H01L2224/05024 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05684 ,  H01L2224/1144 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/12105 ,  H01L2224/13019 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/13166 ,  H01L2224/13184 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/27462 ,  H01L2224/29026 ,  H01L2224/32145 ,  H01L2224/32148 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/81121 ,  H01L2224/81125 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/81895 ,  H01L2224/8191 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/1203 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

Abstract: A method of manufacturing a semiconductor device structure includes forming a bond or joint between a first device and a second device. The first device comprises an integrated passive device (IPD) and a first contact pad disposed over the IPD. The second device comprises a second contact pad. The first contact pad has a first surface with first lateral extents. The second contact pad has a second surface with second lateral extents. The width of the second lateral extents is less than the width of the first lateral extents. The joint structure includes the first contact pad, the second contact pad, and a solder layer interposed therebetween. The solder layer has tapered sidewalls extending in a direction away from the first surface of the first contact pad to the second surface of the second contact pad. At least one of the first surface or the second surface is substantially planar.

公开(公告)号：US20170229431A1

公开(公告)日：2017-08-10

申请号：US15499520

申请日：2017-04-27

Applicant: Cree, Inc.

Inventor： Michael John Bergmann ,  David Todd Emerson ,  Joseph G. Clark ,  Christopher P. Hussell

IPC: H01L25/075 ,  H01L33/48 ,  H01L33/38 ,  H01L33/62 ,  H01L33/50

CPC classification number: H01L25/0756 ,  H01L24/14 ,  H01L24/81 ,  H01L24/94 ,  H01L33/0079 ,  H01L33/0095 ,  H01L33/22 ,  H01L33/38 ,  H01L33/486 ,  H01L33/50 ,  H01L33/507 ,  H01L33/62 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13147 ,  H01L2224/13639 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/1411 ,  H01L2224/14131 ,  H01L2224/14155 ,  H01L2224/14177 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81805 ,  H01L2224/81895 ,  H01L2224/94 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2933/0033 ,  H01L2933/0041 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An LED wafer includes LED dies on an LED substrate. The LED wafer and a carrier wafer are joined. The LED wafer that is joined to the carrier wafer is shaped. Wavelength conversion material is applied to the LED wafer that is shaped. Singulation is performed to provide LED dies that are joined to a carrier die. The singulated devices may be mounted in an LED fixture to provide high light output per unit area.

公开(公告)号：US09685420B2

公开(公告)日：2017-06-20

申请号：US15144108

申请日：2016-05-02

Applicant: Invensas Corporation

Inventor： Rajesh Katkar ,  Cyprian Emeka Uzoh ,  Arkalgud R. Sitaram

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L23/498 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L24/81 ,  H01L21/768 ,  H01L23/49838 ,  H01L23/528 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/10126 ,  H01L2224/1182 ,  H01L2224/13023 ,  H01L2224/13105 ,  H01L2224/13109 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13184 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/1379 ,  H01L2224/13809 ,  H01L2224/13811 ,  H01L2224/13847 ,  H01L2224/13855 ,  H01L2224/1601 ,  H01L2224/16014 ,  H01L2224/16058 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/16503 ,  H01L2224/16507 ,  H01L2224/81007 ,  H01L2224/81048 ,  H01L2224/81143 ,  H01L2224/81193 ,  H01L2224/8181 ,  H01L2224/8182 ,  H01L2224/81862 ,  H01L2224/81895 ,  H01L2224/81903 ,  H01L2224/81905 ,  H01L2224/94 ,  H01L2924/01029 ,  H01L2924/01051 ,  H01L2924/01327 ,  H01L2924/364 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2924/2064

Abstract: An apparatus relates generally to a microelectronic device. In such an apparatus, a first substrate has a first surface with first interconnects located on the first surface, and a second substrate has a second surface spaced apart from the first surface with a gap between the first surface and the second surface. Second interconnects are located on the second surface. Lower surfaces of the first interconnects and upper surfaces of the second interconnects are coupled to one another for electrical conductivity between the first substrate and the second substrate. A conductive collar is around sidewalls of the first and second interconnects, and a dielectric layer is around the conductive collar.