公开(公告)号：US11699639B2

公开(公告)日：2023-07-11

申请号：US17219768

申请日：2021-03-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rafael Jose Lizares Guevara ,  Jovenic Romero Esquejo ,  Arvin Cedric Quiambao Mallari

IPC: H01L23/495 ,  H01L23/00

CPC classification number: H01L23/4952 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/11552 ,  H01L2224/13011 ,  H01L2224/13564 ,  H01L2224/81815

Abstract: In some examples, a quad flat no lead (QFN) semiconductor package comprises a flip chip semiconductor die having a surface and circuitry formed in the surface; and a conductive pillar coupled to the semiconductor die surface. The conductive pillar has a distal end relative to the semiconductor die, the distal end having a cavity including a cavity floor and one or more cavity walls circumscribing the cavity floor. The one or more cavity walls are configured to contain solder.

公开(公告)号：US20230145304A1

公开(公告)日：2023-05-11

申请号：US17749016

申请日：2022-05-19

Applicant: InnoLux Corporation

Inventor： Yi-Hung LIN ,  Chun-Hung LAI ,  Chun-Chin FAN

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L23/49822 ,  H01L24/13 ,  H01L21/4857 ,  H01L21/4853 ,  H01L2224/13021 ,  H01L2224/13144 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/13176 ,  H01L2224/13124 ,  H01L2224/13157 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/1318 ,  H01L2224/13149 ,  H01L2224/13118 ,  H01L2224/13578 ,  H01L2224/13564 ,  H01L2224/13565 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/1369 ,  H01L24/16 ,  H01L2224/16238 ,  H01L2224/1182 ,  H01L24/11 ,  H01L2221/68345 ,  H01L21/6835

Abstract: An electronic device and a method for manufacturing the same are provided. The electronic device includes: a first insulating layer; a first metal bump disposed on the first insulating layer; and a second insulating layer disposed on the first metal bump, wherein the second insulating layer includes a first opening exposing a portion of the first metal bump, wherein a thickness of the first insulating layer is greater than a thickness of the second insulating layer.

公开(公告)号：US20190237434A1

公开(公告)日：2019-08-01

申请号：US16377558

申请日：2019-04-08

Applicant: Micron Technology, Inc.

Inventor： Jaspreet S. Gandhi

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18

CPC classification number: H01L25/0657 ,  H01L24/02 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05155 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05582 ,  H01L2224/05664 ,  H01L2224/06181 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13541 ,  H01L2224/13564 ,  H01L2224/13582 ,  H01L2224/13611 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16058 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16503 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/8181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/00 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/3512 ,  H01L2924/00014

Abstract: Interconnect structures with intermetallic palladium joints are disclosed herein. In one embodiment, an interconnect structure includes a first conductive element, a second conductive element, and an intermetallic palladium joint. The intermetallic palladium joint includes an intermetallic crystallite spanning between the first and second conductive elements. The intermetallic crystallite includes a first end portion and a second end portion. The first end portion directly contacts the first conductive element. The second end portion directly contacts the second conductive element.

公开(公告)号：US09935069B2

公开(公告)日：2018-04-03

申请号：US14392345

申请日：2014-06-05

Applicant: Lumileds LLC

Inventor： Jipu Lei ,  Stefano Schiaffino ,  Alexander H. Nickel ,  Mooi Guan Ng ,  Salman Akram

IPC: H01L23/00 ,  B23K1/20 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L24/11 ,  B23K1/20 ,  H01L21/4853 ,  H01L23/49816 ,  H01L24/03 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L2224/0345 ,  H01L2224/03614 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/06102 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/1182 ,  H01L2224/11825 ,  H01L2224/11826 ,  H01L2224/1184 ,  H01L2224/11845 ,  H01L2224/119 ,  H01L2224/11902 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13147 ,  H01L2224/13564 ,  H01L2224/13582 ,  H01L2224/136 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14104 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81205 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/12041 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/1146 ,  H01L2924/00

Abstract: A technique is disclosed for causing the top surfaces of solder bumps on a chip to be in the same plane to ensure a more reliable bond between the chip and a substrate. The chip is provided with solder pads that may have different heights. A dielectric layer is formed between the solder pads. A relatively thick metal layer is plated over the solder pads. The metal layer is planarized to cause the top surfaces of the metal layer portions over the solder pads to be in the same plane and above the dielectric layer. A substantially uniformly thin layer of solder is deposited over the planarized metal layer portions so that the top surfaces of the solder bumps are substantially in the same plane. The chip is then positioned over a substrate having corresponding metal pads, and the solder is reflowed or ultrasonically bonded to the substrate pads.

公开(公告)号：US09793237B2

公开(公告)日：2017-10-17

申请号：US15085458

申请日：2016-03-30

Applicant: TriQuint Semiconductor, Inc.

Inventor： Tarak A. Railkar ,  Kevin J. Anderson

IPC: H01L23/00

CPC classification number: H01L24/81 ,  H01L21/56 ,  H01L23/3164 ,  H01L23/3185 ,  H01L24/09 ,  H01L24/17 ,  H01L2224/0901 ,  H01L2224/0912 ,  H01L2224/13005 ,  H01L2224/131 ,  H01L2224/13564 ,  H01L2224/13566 ,  H01L2224/1369 ,  H01L2224/16227 ,  H01L2224/1705 ,  H01L2224/17106 ,  H01L2224/81191 ,  H01L2224/812 ,  H01L2224/8121 ,  H01L2224/81355 ,  H01L2224/81375 ,  H01L2224/81385 ,  H01L2224/81395 ,  H01L2224/81815 ,  H01L2224/81862 ,  H01L2224/81905 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2224/81904 ,  H01L2924/206 ,  H01L2924/014

Abstract: The present disclosure relates to a flip-chip package with a hollow-cavity and reinforced interconnects, and a process for making the same. The disclosed flip-chip package includes a substrate, a reinforcement layer over an upper surface of the substrate, a flip-chip die attached to the upper surface of the substrate by interconnects through the reinforcement layer, an air cavity formed between the substrate and the flip-chip die, and a protective layer encapsulating the flip-chip die and defining a perimeter of the air cavity. Herein, a first portion of each interconnect is encapsulated by the reinforcement layer and a second portion of each interconnect is exposed to the air cavity. The reinforcement layer provides reinforcement to each interconnect.

公开(公告)号：US09653336B2

公开(公告)日：2017-05-16

申请号：US15073219

申请日：2016-03-17

Applicant: Amkor Technology, Inc.

Inventor： Yi Seul Han ,  Jae Beum Shim ,  Byong Jin Kim ,  In Bae Park

IPC: H01L21/44 ,  H01L21/683 ,  H01L21/768 ,  H01L23/00 ,  H01L21/288 ,  H01L23/31

CPC classification number: H01L21/6836 ,  H01L21/2885 ,  H01L21/76885 ,  H01L23/3114 ,  H01L23/3192 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/03009 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03614 ,  H01L2224/0391 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/11009 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11848 ,  H01L2224/11849 ,  H01L2224/1191 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1316 ,  H01L2224/13166 ,  H01L2224/13171 ,  H01L2224/13184 ,  H01L2224/1329 ,  H01L2224/13294 ,  H01L2224/133 ,  H01L2224/13562 ,  H01L2224/13564 ,  H01L2224/13566 ,  H01L2224/136 ,  H01L2224/94 ,  H01L2924/01029 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01026 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01074 ,  H01L2924/00014 ,  H01L2224/05147 ,  H01L2924/0665 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/0231

Abstract: An electronic device and a method of making an electronic device. As non-limiting examples, various aspects of this disclosure provide various methods of making electronic devices, and electronic devices made thereby, that utilize a film assist mold process.

公开(公告)号：US20170084564A1

公开(公告)日：2017-03-23

申请号：US15369815

申请日：2016-12-05

Applicant: Intel Corporation

Inventor： Valery M. DUBIN ,  Sridhar BALAKRISHNAN ,  Mark BOHR

IPC: H01L23/00 ,  H01L21/48

CPC classification number: H01L24/13 ,  H01L21/288 ,  H01L21/4853 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11614 ,  H01L2224/13026 ,  H01L2224/13084 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13166 ,  H01L2224/13564 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13647 ,  H01L2224/29111 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2924/35121 ,  H01L2924/3651 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer.

公开(公告)号：US09508668B2

公开(公告)日：2016-11-29

申请号：US14804617

申请日：2015-07-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yen-Liang Lin ,  Yu-Jen Tseng ,  Chang-Chia Huang ,  Tin-Hao Kuo ,  Chen-Shien Chen

IPC: H01L23/00 ,  H01L21/768 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L24/02 ,  H01L21/4853 ,  H01L21/76885 ,  H01L23/49811 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02125 ,  H01L2224/02141 ,  H01L2224/02145 ,  H01L2224/0215 ,  H01L2224/0401 ,  H01L2224/05114 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05647 ,  H01L2224/10125 ,  H01L2224/11013 ,  H01L2224/11019 ,  H01L2224/1112 ,  H01L2224/11462 ,  H01L2224/11472 ,  H01L2224/13012 ,  H01L2224/13015 ,  H01L2224/13017 ,  H01L2224/13023 ,  H01L2224/13026 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13551 ,  H01L2224/13564 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/136 ,  H01L2224/13686 ,  H01L2224/1369 ,  H01L2224/14051 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/16503 ,  H01L2224/81007 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/8181 ,  H01L2224/81895 ,  H01L2224/8192 ,  H01L2224/81948 ,  H01L2225/06513 ,  H01L2924/04941 ,  H01L2924/07025 ,  H01L2924/181 ,  H01L2924/301 ,  H01L2924/35 ,  Y10T29/49144 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/05432 ,  H01L2924/053 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A bump structure includes a contact element formed on a substrate and a passivation layer overlying the substrate. The passivation layer includes a passivation opening exposing the contact element. The bump structure also includes a polyimide layer overlying the passivation layer and an under bump metallurgy (UBM) feature electrically coupled to the contact element. The polyimide layer has a polyimide opening exposing the contact element, and the under bump metallurgy feature has a UBM width. The bump structure further includes a copper pillar on the under bump metallurgy feature. A distal end of the copper pillar has a pillar width, and the UBM width is greater than the pillar width.

Abstract translation: 凸块结构包括形成在衬底上的接触元件和覆盖衬底的钝化层。 钝化层包括暴露接触元件的钝化开口。 凸起结构还包括覆盖钝化层的聚酰亚胺层和电耦合到接触元件的凸块下金属（UBM）特征。 聚酰亚胺层具有暴露接触元件的聚酰亚胺开口，凸起下的金属特征具有UBM宽度。 凸起结构还包括在凸起下金属冶金特征上的铜柱。 铜柱的前端具有柱宽，UBM宽度大于柱宽。

公开(公告)号：US20160218076A1

公开(公告)日：2016-07-28

申请号：US14870377

申请日：2015-09-30

Applicant: Kabushiki Kaisha Toshiba

Inventor： Nobuto MANAGAKI ,  Hiroshi YAMADA

IPC: H01L23/00 ,  H01L23/522 ,  H01L21/48 ,  H01L23/538

CPC classification number: H01L24/13 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/5226 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/82 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/1146 ,  H01L2224/11823 ,  H01L2224/1183 ,  H01L2224/11848 ,  H01L2224/12105 ,  H01L2224/13009 ,  H01L2224/13011 ,  H01L2224/13025 ,  H01L2224/13553 ,  H01L2224/13564 ,  H01L2224/1357 ,  H01L2224/24195 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/19105

Abstract: According to one embodiment, a semiconductor device includes a first conductive portion, a second conductive portion, a first layer, and a second layer. The first conductive portion includes a first end portion and a first extending portion. The first extending portion extends in a first direction. The length of the first extending portion in a second direction is shorter than a length of at least a part of the first end portion in the second direction. The first layer includes multiple semiconductor chips, multiple passive chip components, and a resin. The first extending portion includes a first portion and a second portion. The first layer is provided around the first portion. The first layer expands along a first plane. The first plane intersects the first direction. The second layer includes a first multilayer wiring. The second layer expands along a second plane intersecting the first direction.

Abstract translation: 根据一个实施例，半导体器件包括第一导电部分，第二导电部分，第一层和第二层。 第一导电部分包括第一端部和第一延伸部分。 第一延伸部分在第一方向上延伸。 第一延伸部分在第二方向上的长度短于第一端部在第二方向上的至少一部分的长度。 第一层包括多个半导体芯片，多个无源芯片组件和树脂。 第一延伸部分包括第一部分和第二部分。 第一层围绕第一部分设置。 第一层沿第一平面扩展。 第一个平面与第一个方向相交。 第二层包括第一多层布线。 第二层沿与第一方向相交的第二平面膨胀。

公开(公告)号：US09397062B2

公开(公告)日：2016-07-19

申请号：US14585534

申请日：2014-12-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuei-Wei Huang ,  Wei-Yu Chen ,  Meng-Tse Chen ,  Wei-Hung Lin ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L23/31 ,  H01L21/56 ,  H01L25/03 ,  H01L25/065 ,  H01L25/10 ,  H01L25/00 ,  H01L23/48

CPC classification number: H01L25/105 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/563 ,  H01L23/3135 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/538 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/73 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05557 ,  H01L2224/056 ,  H01L2224/05611 ,  H01L2224/05613 ,  H01L2224/05616 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05684 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13564 ,  H01L2224/136 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16058 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1705 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81007 ,  H01L2224/81193 ,  H01L2224/831 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/01083 ,  H01L2924/00014

Abstract: The described embodiments of mechanisms of forming a die package and package on package (PoP) structure involve forming a solder paste layer over metal balls of external connectors of a die package. The solder paste layer protects the metal balls from oxidation. In addition, the solder paste layer enables solder to solder bonding with another die package. Further, the solder paste layer moves an intermetallic compound (IMC) layer formed between the solder paste layer and the metal balls below a surface of a molding compound of the die package. Having the IMC layer below the surface strengthens the bonding structure between the two die packages.