OVERLAY MEASUREMENT METHOD AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME

    公开(公告)号:US20240219845A1

    公开(公告)日:2024-07-04

    申请号:US18460679

    申请日:2023-09-04

    CPC classification number: G03F7/70633 H01L22/12

    Abstract: An overlay measurement method includes providing a device structure including a substrate, a lower stack on the substrate and an upper stack on the lower stack, measuring a first overlay including critical dimension (CD) information of the device structure, measuring a second overlay including tilt information of the device structure, and calculating a compensation overlay by combining the first overlay and the second overlay, wherein the device structure has a first structure penetrating a portion of at least one of the lower stack or the upper stack in a vertical direction perpendicular to an upper surface of the substrate, and a second structure penetrating a portion of the lower stack and a portion of the upper stack in the vertical direction.

    METHOD OF MEASURING OVERLAY OFFSET AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME

    公开(公告)号:US20240136234A1

    公开(公告)日:2024-04-25

    申请号:US18380691

    申请日:2023-10-17

    CPC classification number: H01L22/12 H01L21/31116

    Abstract: A method of measuring an overlay offset, the method includes: providing a substrate including a lower pattern and an upper pattern, wherein the lower pattern is disposed in a cell area, and the upper pattern is disposed on the lower pattern; acquiring a first piece of overlay information about a first position of the lower pattern and a second position of the upper pattern by detecting a pupil image of a joint position that is between the upper pattern and the lower pattern; detecting an overlay offset of the second position of the upper pattern relative to the first position of the lower pattern through Zernike polynomial modeling; and acquiring compensation overlay information on the upper pattern from the overlay offset of the second position, wherein the overlay offset includes a radial tilting component.

    Overlay correction method and semiconductor fabrication method including the same

    公开(公告)号:US11456222B2

    公开(公告)日:2022-09-27

    申请号:US16886237

    申请日:2020-05-28

    Abstract: An overlay correction method may include obtaining a first central line of a lower pattern on a substrate, forming a photoresist pattern on the lower pattern, obtaining an ADI overlay value corresponding to a first distance between a second central line of an upper flat surface of the lower pattern and a third central line of the photoresist pattern, obtaining an asymmetrical overlay value corresponding to a second distance between the first and second central lines, form an upper pattern using the photoresist pattern, obtaining an ACI overlay value corresponding to a third distance between the first central line and a fourth central line of the upper pattern, subtracting the ADI overlay value from the ACI overlay value to obtain a first overlay skew value, and adding the asymmetrical overlay value to the first overlay skew value to obtain a second overlay skew value.

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